AT90SCR100 datasheet(253/433 Pages) ATMEL

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TPR0327AY–SMS–30Jan09

AT90SCR100

• Bit 0 – UCPOL0: Clock Polarity

This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is

used. The UCPOL0 bit sets the relationship between data output change and data input sample,

and the synchronous clock (XCK).

18.11.5

UBRR0L and UBRR0H – USART Baud Rate Registers

• Bit 15..12 – Reserved Bits

These bits are reserved for future use. For compatibility with future devices, these bit must be

written to zero when UBRRH is written.

• Bit 11..0 – UBRR11..0: USART Baud Rate Register

This is a 12-bit register which contains the USART baud rate. The UBRRH contains the four

most significant bits, and the UBRRL contains the eight least significant bits of the USART baud

rate. Ongoing transmissions by the Transmitter and Receiver will be corrupted if the baud rate is

changed. Writing UBRRL will trigger an immediate update of the baud rate prescaler.

101

Reserved

110

Reserved

111

9-bit

Table 18-8.

UCPOLn Bit Settings

UCPOL0

Transmitted Data Changed (Output of

TxD0 Pin)

Received Data Sampled (Input on RxD0

Pin)

Rising XCK Edge

Falling XCK Edge

Rising XCK Edge

Table 18-7.

UCSZ0 Bits Settings

UCSZ02

UCSZ01

UCSZ00

Character Size

Bit

7654

$0000C5

----

UBRR[11..8]

UBRRH0

$0000C4

UBRR[7..0]

UBRRL0

Read/write

RRRR

R/W

Initial value

0000

0x00

0000

0x00

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