AT90SCR100 datasheet(252/433 Pages) ATMEL

252 / 433 page

252

TPR0327AY–SMS–30Jan09

AT90SCR100

Note:

1. See “USART in SPI Mode” on page 257 for full description of the Master SPI Mode (MSPIM)

operation

• Bits 5..4 – UPM01..0: Parity Mode

These bits enable and set type of parity generation and check. If enabled, the Transmitter will

automatically generate and send the parity of the transmitted data bits within each frame. The

Receiver will generate a parity value for the incoming data and compare it to the UPM0 setting.

If a mismatch is detected, the UPE0 Flag in UCSR0A will be set.

• Bit 3 – USBS0: Stop Bit Select

This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores

this setting.

• Bit 2:1 – UCSZ01:0: Character Size

The UCSZ01:0 bits combined with the UCSZ02 bit in UCSR0B sets the number of data bits

(Character size) in a frame the Receiver and Transmitter use.

Synchronous USART

(Reserved)

Master SPI (MSPIM)(1)

Table 18-5.

UPM0 Bits Settings

UPM01

UPM00

Parity Mode

Disabled

Reserved

Enabled, Even Parity

Enabled, Odd Parity

Table 18-6.

USBS Bit Settings

USBS0

Stop Bit(s)

01-bit

12-bit

Table 18-7.

UCSZ0 Bits Settings

UCSZ02

UCSZ01

UCSZ00

Character Size

000

5-bit

001

6-bit

010

7-bit

011

8-bit

100

Reserved

Table 18-4.

UMSEL0 Bits Settings

UMSEL01

UMSEL00

Mode

AT90SCR100 bảng dữ liệu(PDF) 252 Page - ATMEL Corporation

AT90SCR100 bảng dữ liệu(HTML) 252 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL