AT90SCR100 datasheet(213/433 Pages) ATMEL

213 / 433 page

213

TPR0327AY–SMS–30Jan09

AT90SCR100

Once the downstream Resume has been generated, the UHCR.SOFE bit is automatically set by

hardware in order to generate SOF immediately after the USB resume.

17.5.9

USB Pipe Reset

The firmware can reset a Pipe using the pipe reset register. The configuration of the pipe and

the data toggle remains unchanged. Only the bank management and the status bits are reset to

their initial values.

To completely reset a Pipe, the firmware has to disable and then enable the pipe.

17.5.10

Pipe Data Access

In order to read or to write into the Pipe Fifo, the CPU selects the Pipe number with the UPNUM

17.5.11

Control Pipe management

A Control transaction is composed of 3 phases:

•SETUP

• Data (IN or OUT)

• Status (OUT or IN)

The firmware has to change the Token for each phase.

The initial data toggle is set for the corresponding token (ONLY for Control Pipe):

• SETUP: Data0

• OUT: Data1

• IN: Data1 (expected data toggle)

17.5.12

OUT Pipe management

The Pipe must be configured and not frozen first.

17.5.12.1

“Manual” mode

The UPINTX.TXOUTI bit is set by hardware when the current bank becomes free. This triggers

an interrupt if the UPIENX.TXOUTE bit is set. The UPINTX.FIFOCON bit is set at the same time.

The CPU writes into the FIFO and clears the UPINTX.FIFOCON bit to allow the USB controller

to send the data.

If the OUT Pipe is composed of multiple banks, this also switches to the next data bank. The

UPINTX.TXOUTI and UPINTX.FIFOCON bits are automatically updated by hardware regarding

the status of the next bank.

Host

Ready

UHCR.SOFE=1

or UHINT.HWUPI=1

UHCR.SOFEN=0

Host

Suspend

If the firmware decides to switch to suspend mode (clear UHCR.SOFEN) even if a

bank is ready to be sent, the USB controller will automatically exit from Suspend

mode and the bank will be sent.

Note

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