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S32K310 bảng dữ liệu(PDF) 108 Page - NXP Semiconductors |
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S32K310 bảng dữ liệu(HTML) 108 Page - NXP Semiconductors |
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108 / 164 page  SAI_TXD SAI_RXD SAI_FS (output) SAI_BCLK (output) S6 S7 S11 S4 S3 S1 S4 S9 S8 S8 S7 S5 SAI_MCLK (input) SAI_FS (input) S10 S12 S2 S2 Figure 52. SAI controller mode 12.8 Ethernet characteristics 12.8.1 Ethernet MII (10/100 Mbps) The following timing specs are defined at the device I/O pin and must be translated appropriately to arrive at timing specs/ constraints for the physical interface. Measurements are with maximum output load of 25pF, input transition of 1ns and pad configured with DSE = 1'b1 and SRE = 1'b0. I/O operating voltage ranges from 2.97 V to 3.63 V. Valid pin combinations to be referred from K3xx*_Use sheet in IOmux. Table 56. Ethernet MII (10/100 Mbps) Symbol Description Min Typ Max Unit Condition Spec Number — RXCLK frequency — 2.5/25 — MHz 10/100 Mbps — MII1 RXCLK pulse width high 35 — 65 %RXCLK period — — MII2 RXCLK pulse width low 35 — 65 %RXCLK period — — MII3 RXD[3:0], RXDV, RXER to RXCLK setup 5 — — ns 10/100 Mbps — MII4 RXCLK to RXD[3:0], RXDV, RXER hold 5 — — ns 10/100 Mbps — tCYC_TX TXCLK frequency — 2.5 / 25 — MHz 10/100 Mbps — MII5 TXCLK pulse width high 35 — 65 %TXCLK period — — MII6 TXCLK pulse width low 35 — 65 %TXCLK period — — Table continues on the next page... NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product data sheet Rev. 13 — 12 November 2025 Document feedback 108 / 164 |
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