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S32K310 bảng dữ liệu(PDF) 10 Page - NXP Semiconductors |
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S32K310 bảng dữ liệu(HTML) 10 Page - NXP Semiconductors |
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10 / 164 page  Xbar (64 bit) Fabric 6 MB Pflash with ECC Memory External Memory IF 1 x Ethernet, 1 Gbps AVB/TSN 8 x FlexCAN all ch support CAN FD 16 x LPUART (LIN) Network 32 ch FlexIO Emulating UART, I2C, SPI I2S, SENT, PWM Communication 128 kB Dflash with ECC 1152 kB RAM with ECC Include 384 kB TCM FXOSC (8-40 MHz) Memory OTA ready - RWW, A/B swap External Flash/Ram expansion by QuadSPI • • CPU Platform Arm M7 cores in lockstep One independent Arm M7 for real time processing Optimized for Real- time with zero wait I/D-TCM • • • Motor Control On-chip motor control subsystem Offloading CPU • • Future Proof Security/OTA ISO26262 Compliant Safety System Scalable Arm platform Optimized for LOW power Rich Network/Communication Interface • • • • • Safety HW redundancy MBIST/LBIST/Self Test Clock/Voltage monitor Centralized error detection ASIL D compliant • • • • • Security HW accl for AES 256, RSA 4096, ECC 521 Firmware included, upgradable Side-channel physical protection Meet Evita Full function goal • • • • Network/ Communication Ethernet (TSN), CAN/ CAN FD, LIN SAI for Audio Flexible IO emulation • • • System FIRC (48 MHz) CPU Platform Cortex-M7 240 MHz FPU, DSP I-cache D-cache Cortex-M7 240 MHz FPU, DSP I-cache D-cache Lockstep Core SIRC (32 kHz) SXOSC (32 kHz) 2 x PLL 32ch DMA 32ch ext. INT/WKUP 6 x LPSPI 2 x LPI2C 2 x SAI (TDM, I2S) Analog/Timers BCTU (Body Control Trigger Unit) 3 x 24 ch 12 bit ADC LCU (Logic Control Unit) 3 x 24 ch 16 bit eMIOS Timer 3 x LPCMP Functional Safety CMU FCCU MPU SWT EIM/ERM STCU2 CRC Security: HSE-B Cortex-M0+ RAM XRDC Access control Lifecycle Management Asymmetric Hardware Accelerators Symmetric Hardware Accelerators TRNG/PRNG Debug/Trace (SWD/JTAG/ETB) Cortex-M7 240 MHz FPU, DSP I-cache D-cache 1 x uSDHC 32 bit RTC 1 x QuadSPI Upto 2 Gbps 8 bit data width Figure 14. S32K356: ASIL D Lockstep Core + One, 6MB General Purpose MCU Fabric Memory 8 MB Pflash with ECC 128 KB Dflash with ECC 1152 KB RAM with ECC Incl 384 KB TCM System Debug/Trace (SWD/JTAG/ETB) FXOSC (8 - 40MHz) 32ch ext. INT/WUP Security: HSE -B Asymmetric Hardware Accelerators Symmetric Hardware Accelerators Lifecycle Management XRDC Access control FIRC (48MHz) SIRC (32KHz) SXOSC (32KHz) 2 x PLL 32ch DMA Analog/Timers 3 x 24ch 12bit ADC 3x24ch 16bit eMIOS Timer BCTU (Body Control Trigger Unit) LCU (Logic Control Unit) MPU CRC FCCU EIM/ERM SWT Functional Safety CMU STCU External Memory IF Communication 6 x LPSPI 2 x LPI2C 2 x SAI (TDM, I2S) Network 8 x FlexCAN, all ch support CAN FD 2 x Ethernet, 1Gbps AVB/TSN Xbar (64bit) Cortex- M0+ RAM 32ch FlexIO Emulating UART, I2C, SPI, I2S, SENT, PWM 16 x LPUART (LIN) TRNG/PRNG 3x LPCMP CPU Platform Lock- Step or Split- Lock Permanent Lock AES Accelerator Dedicated to Communications AES Accelerator optimized for Low Latency Performance Cortex-M7 300 MHz FPU, DSP I-cache D-cache Cortex-M7 320 MHz FPU, DSP I-cache D-cache Cortex-M7 320 MHz FPU, DSP I-cache D-cache Cortex-M7 320 MHz FPU, DSP I-cache D-cache Cortex-M7 320 MHz FPU, DSP I-cache D-cache 32 bit RTC 1 x QuadSPI 4 bit data width Figure 15. S32K388: ASIL D 8MB MCU Fabric Memory 12MB PflashwithECC 256 KB Dflash with ECC 2.25MB SRAM with ECC System Debug/Trace (SWD/JTAG/ETB) FXOSC(8-40MHz) 32ch ext.INT/WUP Security: HSE-B Asymmetric Hardware Accelerators Symmetric Hardware Accelerators Lifecycle Management XRDC Access control FIRC(48MHz) SIRC(32KHz) SXOSC (32KHz) PLL 32ch DMA Analog/Timers 3 x 24ch12bit ADC 3x24ch 24bit eMIOSTimer BCTU (Body Control Trigger Unit) LCU (Logic Control Unit) MPU CRC FCCU EIM/ERM SWT FunctionalSafety CMU STCU ExternalMemoryIF 1 x QuadSPI 4bit data width Communication 6 x LPSPI 2 x LPI2C 2 x SAI (TDM,I2S) Network 12xFlexCAN, all ch support CAN FD 2 x Ethernet,1Gbps AVB/TSN Xbar (64bit) Cortex-M0+ RAM 32ch FlexIO Emulating UART, I2C, SPI, I2S, SENT,PWM 16 x LPUART (LIN) TRNG/PRNG 3x LPCMP CPU Platform Cortex-M7 32kB I-cache NEON 32kB D- 32kB TCM32kB TCM Cortex-M7 16 KB I-cache 16 KB D-cache TCM: 32K-I, 64K-D Cortex-M7 16 KB I-cache 16 KB D-cache TCM: 32K-I, 64K-D DP-FPU, DSP DP-FPU, DSP Lock-Stepor Split-Lock PermanentLock 16 KB I-cache Cortex-M7 32 KB I- 32 KB D-cache TCM: 32K-I, 64K-D DP-FPU, DSP 16 KB I-cache 16 KB D-cache 16 KB I-cache Cortex-M7 32 KB I-cache 32 KB D-cache TCM: 32K-I, 64K-D DP-FPU, DSP 16 KB I-cache 16 KB D- 16 KB I-cache AES Accelerator Dedicatedto Communications +FLEXCANs +FLASH +SRAM 437BGA Package Figure 16. S32K389: ASIL D 12MB MCU NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product data sheet Rev. 13 — 12 November 2025 Document feedback 10 / 164 |
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