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S32K310 bảng dữ liệu(PDF) 71 Page - NXP Semiconductors

tên linh kiện S32K310
Giải thích chi tiết về linh kiện  Supports S32K344, S32K324, S32K314, S32K312, S32K311, S32K310, S32K341, S32K342, S32K322, S32K328, S32K338, S32K348, S32K356, S32K358, S32K388 and S32K389. Data is preliminary for S32K312 and S32K344 100LQFP only.
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Table 27. GPIO DC electrical specifications, 3.3V Range (2.97V - 3.63V)...continued
Symbol
Description
Min
Typ
Max
Unit
Condition
Spec
Number
FMAX_33_F
3.3V maximum
frequency for Fast
GPIO [5][7]
—
—
125
MHz
2.9V - 3.6V, CL (max)
= 25pF, for S32K3x8
and S32K389 devices
—
IOHT
Output high current
total for all ports [8]
—
—
100
mA
—
—
[1] Maximum length of RESET pulse will be filtered by an internal filter on this pin.
[2] Minimum length of RESET pulse, guaranteed not to be filtered by the internal filter.
[3] A positive value is leakage flowing into pin with pin at VDD_HV_A/B (the GPIO supply level); a negative value is leakage flowing out the pin with the pin at
ground.
[4] Hysteresis spec does not apply to fast pad
[5] GPIO output transition time information can be obtained from the device IBIS model. IBIS models are recommended for system level simulations, as discrete
values for I/O transition times are not representative of the I/O pad behavior when connected to an actual transmission line load.
[6] I/O output current specifications are valid for the given reference load figure, and the constraints given in the Operating Conditions of this document.
[7] I/O timing specifications are valid for the un-terminated 50ohm transmission line reference load given in the figure below. A lumped 8pF load is assumed
in addition to a 5 inch microstrip trace on standard FR4 with approximately 3.3pF/inch. For signals with frequency greater than 63MHz, a maximum 2 inch
PCB trace is assumed. For best signal integrity, the series resistance in the transmission line should be matched closely to the selected output resistance
(ROUT_*) of the I/O pad.
[8] To determine total switching current on any I/O supply, current values per output pin should not be incrementally summed. I/O interfaces on the device are
asynchronous to each other, so not all switching occurs at the same instant. Actual use case must be considered.
RDSON
RPCB = RDSON
PCB
External
device
MCUsee note 1
RDSON
5 in.
(4 layer FR4)
CPCB = ~3.3 pF/inch * 5 inch
CL = 8 pF
1. See IBIS models for further details.
Notes:
Figure 34. Reference Load Diagram
7.2 GPIO DC electrical specifications, 5.0V (4.5V - 5.5V)
The leakage current on the GPIO pins is specified as a function of the pad type (Standard, Standard Plus, Medium, Fast, or GPI)
and the number of Analog functions (CMP and ADC channels) multiplexed per pin.
For S32K388, see the ILKG column in the Pinout section of the IOMUX file attached to the Reference Manual.
For other devices, the "Analog Function Count" is defined from the number of CMP and ADC channels multiplexed to a given
pin. This information can be obtained from the "Direct Signals" column in the IOMUX files attached to the Reference Manual. The
"Analog Function Count" is shown in the Condition column of the following table.
Table 28. GPIO DC electrical specifications, 5.0V (4.5V - 5.5V)
Symbol
Description
Min
Typ
Max
Unit
Condition
Spec
Number
VIH
Input high level DC
voltage threshold
0.65 x
VDD_HV
_A/B
—
VDD_HV
_A/B +
0.3
V
VDD_HV_A/B = 5.0V
—
Table continues on the next page...
NXP Semiconductors
S32K3XX
S32K3xx Data Sheet
S32K3XX
All information provided in this document is subject to legal disclaimers.
© 2025 NXP B.V. All rights reserved.
Product data sheet
Rev. 13 — 12 November 2025
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