S32K310 datasheet(94/164 Pages) NXP

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Crystal oscillator circuit provides stable oscillations when gmXOSC > 5 * gm_crit. The gm_crit is defined as:

gm_crit = 4 * (ESR + RS) * (2πF)2 * (C0 + CL)2

where:

• gmXOSC is the transconductance of the internal oscillator circuit

• ESR is the equivalent series resistance of the external crystal

• RS is the series resistance connected between XTAL pin and external crystal for current limitation

• F is the external crystal oscillation frequency

• C0 is the shunt capacitance of the external crystal

• CL is the external crystal total load capacitance. CL = Cs+ [C1*C2/(C1+C2)]

• Cs is stray or parasitic capacitance on the pin due to any PCB traces

• C1, C2 external load capacitances on EXTAL and XTAL pins

See manufacture datasheet for external crystal component values

Figure 44. Oscillation build-up equation

Note: To improve the FXOSC & PLL jitter performance in S32K328, S32K338, S32K348, S32K356, S32K358 the functionality of

the pins (namely - PTG0,PTG3,PTF11,PTF19,PTF30, PMOS_CTRL in BGA289 package) cannot be toggling edge aligned.

Note: To improve the FXOSC jitter & duty cycle performance in S32K310, S32K311, S32K312, S32K322, S32K341 S32K342,

S32K314,S32K324 and S32K344, the functionality of the pin next to the Oscillator (namely, PTE14 in HDQFP172 and PTE3 in

HDQFP100 package) must be limited to static GPIO operation.

Note: To improve the FXOSC & PLL jitter performance in S32K388, the functionality of the pins (namely - PTG0, PTG2, PTG3,

PTF30, PTE12, PTA29, PMOS_CTRL in BGA289 package) cannot be toggling edge-aligned.

Note: To improve the FXOSC & PLL jitter performance in S32K389, the functionality of the pins (namely - PTE3, PTD15, PTE8,

PTE4, PTG6, PTG0 and PMOS_CTRL in BGA437 package) cannot be toggling edge-aligned.

NXP Semiconductors

S32K3XX

S32K3xx Data Sheet

S32K3XX

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Product data sheet

Rev. 13 — 12 November 2025

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