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S32K310 bảng dữ liệu(PDF) 64 Page - NXP Semiconductors |
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S32K310 bảng dữ liệu(HTML) 64 Page - NXP Semiconductors |
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64 / 164 page  Table 23. RUN mode configuration options...continued MODU LE Min. Config. (Optio nF[1]), PLL@ 80 MHz Min. Config. (Optio nB[1]), PLL@ 120 MHz Min. Config. (Optio nA[1]), PLL@ 160 MHz Min. Config. (Optio nA+[1]), PLL@ 240 MHz Min. Config. (Optio nA+ +[1]), PLL@ 320 MHz Config. 1 Dual Core @160 MHz Config. 2 Single Core @160 MHz Config. 3 Dual Core @120 MHz Config. 4 Single Core @120 MHz Config. 5 Single Core @80M Hz Config. 6-1 Dual Core @240 MHz Config. 6-2 Triple Core @240 MHz Config. 7 1xLS + 3x cores @320 MHz LPUA RT[4] All OFF All OFF All OFF All OFF All OFF 16x 4x 10x 8x 7x 16x 16x 16x LPSPI[ 5] All OFF All OFF All OFF All OFF All OFF 6x 4x 4x 4x 3x 5x 5x 5x LPI2C[ 6] All OFF All OFF All OFF All OFF All OFF All OFF 2x 2x 2x All OFF 1x 1x 1x EMAC/ GMAC[ 7] OFF OFF OFF OFF OFF ON OFF ON OFF OFF ON ON ON SAI OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF QSPI OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF ON ON ON eMIOS [8] All OFF All OFF All OFF All OFF All OFF All OFF 3x 3x 2x 2x 2x 2x 2x SAR_A DC[9] All OFF All OFF All OFF All OFF All OFF All OFF 3x 3x 2x 2x 3x 3x 3x LPCM P[10] All OFF All OFF All OFF All OFF All OFF All OFF 2x 3x All OFF All OFF OFF OFF OFF [1] See clocking use case examples in the Clocking chapter of the S32K3xx Reference Manual. [2] HSE_B: After start-up, the HSE core is in WFI. [3] • FlexCAN0: Transmitting an 8-byte CAN-FD data frame at 5 Mbps, every 10 ms. • FlexCAN1: Transmitting a 64-byte CAN-FD data frame at 2 Mbps, every 20 ms. • FlexCAN2-5: Transmitting an 8-byte CAN data frame at 500 Kbps, every 20 ms. [4] LPUART0-15: Transmitting at 19200 bps, every 100ms. [5] • LPSPI0: Transmitting 32 bits at 20 Mbps (GPIO Fast pads), every 5 ms. • LPSPI1-5: Transmitting 32 bits at 1 Mbps, every 5 ms. [6] LPI2C0-1: Transmitting 3 bytes at 400 Kbps, every 100ms. [7] EMAC/GMAC: ON for MII interface. [8] • eMIOS0: 6 channels in PWM mode @ 20 KHz. • eMIOS1-2: 8 channels in PWM mode @ 400 Hz. [9] • SAR_ADC0: 16 channels at 400 Hz rate, BCTU triggered. • SAR_ADC1-2: 4 channels at 20 KHz rate, BCTU triggered. [10] LPCMP0: 8 channels enabled; LPCMP1-2: 4 channels enabled. NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product data sheet Rev. 13 — 12 November 2025 Document feedback 64 / 164 |
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