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S32K310 bảng dữ liệu(PDF) 92 Page - NXP Semiconductors |
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92 / 164 page  Table 44. PLL...continued Symbol Description Min Typ Max Unit Condition Spec Number JPLL_acc PLL accumulated jitter (pk-pk) [2][3][4] — — 1680 ps FPLL_out = 240MHz, Fractional Mode — JPLL_cyc PLL period jitter (pk- pk) [2][3][4] — — 295 ps FPLL_out = 160MHz, Integer Mode — JPLL_cyc PLL period jitter (pk- pk) [2][3][4] — — 670 ps FPLL_out = 160MHz, Fractional Mode — JPLL_acc PLL accumulated jitter (pk-pk) [2][3][4] — — 840 ps FPLL_out = 160MHz, Integer Mode — JPLL_acc PLL accumulated jitter (pk-pk) [2][3][4] — — 1680 ps FPLL_out = 160MHz, Fractional Mode — JPLL_cyc PLL period jitter (pk- pk) [2][3][4] — — 353 ps FPLL_out = 120MHz, Integer Mode — JPLL_cyc PLL period jitter (pk- pk) [2][3][4] — — 853 ps FPLL_out = 120MHz, Fractional Mode — JPLL_acc PLL accumulated jitter (pk-pk) [2][3][4] — — 840 ps FPLL_out = 120MHz, Integer Mode — JPLL_acc PLL accumulated jitter (pk-pk) [2][3][4] — — 1680 ps FPLL_out = 120MHz, Fractional Mode — [1] The PLL output frequency must be configured such that the clock driven by this PLL output does not exceeded the maximum allowed for each device (see the Clocking chapter of the Reference Manual). [2] Jitter numbers are valid only at IP boundary and does not include any degradation due to IO pad for clock measurement. [3] Jitter numbers calculated by extrapolating RMS jitter numbers to +/- 7 sigma . [4] For SSCG, jitter due to systematic modulation needs to be added as per applied modulation. Accumulated jitter specification is not valid with SSCG 11.4 FXOSC Table 45. FXOSC Symbol Description Min Typ Max Unit Condition Spec Number FREQ_BYPASS Input clock frequency in bypass mode [1] — — 50 MHz — — TRF_BYPASS Input clock rise/fall time in bypass mode [1] — — 5 ns — — CLKIN_DUTY_ BYPASS Input clock duty cycle in bypass mode [1] 47.5 — 52.5 % — — FXOSC_CLK output clock frequency in crystal mode 8 — 40 MHz — — Table continues on the next page... NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product data sheet Rev. 13 — 12 November 2025 Document feedback 92 / 164 |
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