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S32K310 bảng dữ liệu(HTML) 88 Page - NXP Semiconductors |
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88 / 164 page  Table 40. Low Power Comparator (LPCMP)...continued Symbol Description Min Typ Max Unit Condition Spec Number DNL DAC differential linearity [1][7] -1.5 — 1.5 LSB vrefh_cmp < vdda — tDDAC DAC Initialization time — — 30 us — — VAIN Analog input voltage 0 — VDDA V — — [1] vdda is comparator HV supply and internally shorted to VDD_HV_A pin. vss is comparator ground [2] Difference at input > 200mV [3] Applied +/- (100 mV + VAHYST0/1/2/3 + max. of VAIO) around switch point [4] Applied +/- (30 mV + VAHYST0/1/2/3 + max. of VAIO) around switch point [5] Applied ± (100 mV + VAHYST0/1/2/3 ). [6] Calculation method used: Linear Regression Least Square Method [7] 1 LSB = (vrefh_cmp - vrefl_cmp) /256. vrefh_cmp and vrefl_cmp are comparator reference high and low For Comparator IN signals adjacent to VDD_HV_A/VDD_HV_B/VSS or XTAL/EXTAL or switching pins cross coupling may happen and hence hysteresis settings can be used to obtain the desired Comparator performance. Additionally an external capacitor to ground (1nF) should be used to filter noise on input signal. Also source drive should not be weak (Signal with <50K pull up/down is recommended). For devices where the VDD_HV_B domain is present, LPCMP0 channels must only be selected/enabled when VDD_HV_A >= VDD_HV_B. These channels must be disabled when VDD_HV_A goes below VDD_HV_B. See GPIO test conditions before applying LPCMP channel input reference. 0 3.3 3.0 1.5 2.1 0.6 30 60 Hysteresis (mV) 0 VAIN (V) Junction Temp (°C) VDD_HV_A (V) HYSTCTR setting 0.3 1.2 2.4 2.7 0.9 1.8 3.3 25 90 00 01 10 11 Figure 40. Typical Hysteresis vs VAIN (VDD_HV_A = 3.3 V, High Speed Mode) NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product data sheet Rev. 13 — 12 November 2025 Document feedback 88 / 164 |
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