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S32K310 bảng dữ liệu(PDF) 82 Page - NXP Semiconductors

tên linh kiện S32K310
Giải thích chi tiết về linh kiện  Supports S32K344, S32K324, S32K314, S32K312, S32K311, S32K310, S32K341, S32K342, S32K322, S32K328, S32K338, S32K348, S32K356, S32K358, S32K388 and S32K389. Data is preliminary for S32K312 and S32K344 100LQFP only.
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9.4 Flash memory AC timing specifications
Table 35. Flash memory AC timing specifications
Symbol
Characteristic
Min
Typical
Max
Units
tdone
Time from 0 to 1 transition on the MCR[EHV] bit
initiating a program/erase until the MCR[DONE]
bit is cleared.
—
—
5
ns
tdones
Time from 1 to 0 transition on the MCR[EHV] bit
aborting a program/erase until the MCR[DONE]
bit is set to a 1.
5 plus four
system clock
periods
—
22 plus four
system clock
periods[1]
µs
tdrcv
Time to recover once exiting low power mode.
14 plus seven
system clock
periods[2]
17.5 plus
seven system
clock periods
21 plus seven
system clock
periods
µs
taistart
Time from 0 to 1 transition of UT0[AIE] initiating a
Margin Read or Array Integrity until the UT0[AID]
bit is cleared. This time also applies to the
resuming from a suspend or breakpoint by
clearing UT0[AISUS] or clearing UT0[NAIBP]
—
—
5
ns
taistop
Time from 1 to 0 transition of UT0[AIE] initiating
an Array Integrity abort until the UT0[AID] bit is
set. This time also applies to the UT0[AISUS] to
UT0[AID] setting in the event of a Array Integrity
suspend request.
—
—
50
system clock
periods
ns
tmrstop
Time from 1 to 0 transition of UT0[AIE] initiating
a Margin Read abort until the UT0[AID] bit is
set. This time also applies to the UT0[AISUS] to
UT0[AID] setting in the event of a Margin Read
suspend request.
—
—
26
plus fifteen
system clock
periods
µs
[1] For Block Erase, Tdones times may be 3x max spec.
[2] In extreme cases (1 block configurations) Tdrcv min may be faster (12uS plus seven system clocks)
9.5 Flash memory read timing parameters
Table 36. Flash Read Wait State Settings (S32K344, S32K324, S32K314, S32K342, S32K322, S32K341, S32K312,
S32K311, S2K310 and S32K389(PFC1))
Flash Frequency (CORE_CLK)
RWSC setting
250 KHz < Freq ≤ 66 MHz
1
66 MHz < Freq ≤ 100 MHz
2
100 MHz < Freq ≤ 133 MHz
3
133 MHz < Freq ≤ 167 MHz
4
167 MHz < Freq ≤ 200 MHz
5
Table continues on the next page...
NXP Semiconductors
S32K3XX
S32K3xx Data Sheet
S32K3XX
All information provided in this document is subject to legal disclaimers.
© 2025 NXP B.V. All rights reserved.
Product data sheet
Rev. 13 — 12 November 2025
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