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S32K310 bảng dữ liệu(PDF) 91 Page - NXP Semiconductors |
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S32K310 bảng dữ liệu(HTML) 91 Page - NXP Semiconductors |
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91 / 164 page ![]() 11.2 SIRC Table 43. SIRC Symbol Description Min Typ Max Unit Condition Spec Number fSIRC SIRC nominal Frequency — 32 — KHz — — fSIRC_ACC SIRC Frequency deviation across process, voltage, and temperature after trimming -10 — 10 % — — TSIRC_start SIRC Startup Time [1] — — 3 ms — — TSIRC_DC SIRC duty cycle 30 — 70 % — — [1] Startup time is for information only. 11.3 PLL FPLL_DS, FPLL_FM and all fractional mode jitter specifications are not applicable to Auxiliary PLL on S32K328, S32K338, S32K348, S32K356, S32K358, S32K388 and S32K389 devices. Jitter values specified in this table are applicable for FXOSC reference clock input only. Table 44. PLL Symbol Description Min Typ Max Unit Condition Spec Number FPLL_in PLL input frequency 8 — 40 MHz This is the frequency after the Reference Divider within the PLL — FPLL_out PLL output frequency (PLL_PHIn_CLK) [1] 25 — 500 MHz — — FPLL_vcoRange VCO Frequency range 640 — 1280 MHz — — FPLL_DS Modulation Depth (down spread) -0.5 — -3 % — — FPLL_FM Modulation frequency — — 32 KHz — — TPLL_start PLL lock time — — 1 ms — — JPLL_cyc PLL period jitter (pk- pk) [2][3][4] — — 237 ps FPLL_out = 240MHz, Integer Mode — JPLL_cyc PLL period jitter (pk- pk) [2][3][4] — — 487 ps FPLL_out = 240MHz, Fractional Mode — JPLL_acc PLL accumulated jitter (pk-pk) [2][3][4] — — 840 ps FPLL_out = 240MHz, Integer Mode — Table continues on the next page... NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product data sheet Rev. 13 — 12 November 2025 Document feedback 91 / 164 |
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