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S32K310 bảng dữ liệu(PDF) 16 Page - NXP Semiconductors |
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S32K310 bảng dữ liệu(HTML) 16 Page - NXP Semiconductors |
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16 / 164 page ![]() Table 1. S32K3xx chip's feature comparison...continued Feature Chip 172- HDQFP package No Yes No 172- HDQFP - EP package No Yes No 100- HDQFP package Yes No 100- LQFP package No Yes No Yes No 48-pin LQFP package Yes No [1] ASIL-B and ASIL-D performance is available simultaneously. ASIL-D performance can also be used for ASIL-B performance. [2] The first result abides by all of the "ground rules" out in Dhrystone documentation, the second permits inlining of functions, not just permitted C strings libraries, while the third additionally permits simultaneous ("multi-file") compilation. All are with the original (K and R) v2.1 of Dhrystone. Arm Compiler 6.17. See https://developer.arm.com/Processors/Cortex-M7 for details. [3] Core configuration is 2xLS + 1 independent core [4] Core configuration is 1xLS + 3 independent cores [5] Results depends on specific compiler version, contact NXP sales representative for more details. [6] 4-bit data width, SDR mode only [7] 8-bit data width, SDR and DDR mode NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product data sheet Rev. 13 — 12 November 2025 Document feedback 16 / 164 |
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