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S32K310 bảng dữ liệu(HTML) 104 Page - NXP Semiconductors |
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104 / 164 page  Table 52. Pins and signals assignment for this communication....continued PCS PTG23 LPSPI5_PCS0 PCS PTG28 LPSPI5_PCS0 SCK PTD31 LPSPI5_SCK SCK PTG31 LPSPI5_SCK D0 PTG25 LPSPI5_SOUT D0 PTG30 LPSPI5_SOUT D1 PTD28 LPSPI5_SIN D1 PTG29 LPSPI5_SIN D2 PTG24 LPSPI5_PCS2 D2 PTG13 LPSPI5_PCS2 D3 PTD30 LPSPI5_PCS3 D3 PTG8 LPSPI5_PCS3 12.4.1 Timing specification for S32K38x to S32K38x communication Below table lists the timing parameters for this communication. This parameters is valid only on set of pins preselected for this device to device communication. All timing is shown with respect to 50% VDD_HV_A/B thresholds. All measurements are with maximum output load of 50 pF, input transition of 1 ns and pad configured with fastest slew setting (DSE = 1'b1). Table 53. Timing specification for S32K38x to S32K38x communication Symbol Description Min Typ Max Unit Condition Spec Number fcom Communication frequency — — 6.6 MHz — — tWSPCK Clock (SPSCK) high or low time (SPSCK duty cycle) 69 — 79 ns — — tSU Data setup time 34 — — ns Controller mode 6 tSU Data setup time 5 — — ns Peripheral mode 6 tV Data valid (after SPSCK edge) — — 21 ns Controller mode 10 tV Data valid (after SPSCK edge) — — 34 ns Peripheral mode 10 tHO Input hold time 0 — — ns Controller mode input 7 tHO Input hold time 4 — — ns Peripheral mode input 7 tHO Output hold time 3 — — ns Peripheral mode output 11 tHO Output hold time -15 — — ns Controller mode output 11 tLEAD Enable lead time (PCS to SPSCK delay) 30 — — ns Controller mode 3 tA Peripheral access time — — 50 ns — — tDIS Peripheral MISO (SOUT) disable time — — 50 ns — — tLAG Enable lag time (After SPSCK delay) 30 — — ns — — NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product data sheet Rev. 13 — 12 November 2025 Document feedback 104 / 164 |
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