APEX20KC datasheet(19/90 Pages) ALTERA

19 / 90 page

Altera Corporation

APEX 20KC Programmable Logic Device Data Sheet

The counter mode uses two 3-input LUTs: one generates the counter data,

and the other generates the fast carry bit. A 2-to-1 multiplexer provides

synchronous loading, and another AND gate provides synchronous

clearing. If the cascade function is used by an LE in counter mode, the

synchronous clear or load overrides any signal carried on the cascade

chain. The synchronous clear overrides the synchronous load. LEs in

arithmetic mode can drive out registered and unregistered versions of the

LUT output.

Clear & Preset Logic Control

Logic for the register’s clear and preset signals is controlled by LAB-wide

signals. The LE directly supports an asynchronous clear function. The

Quartus II Compiler can use a NOT-gate push-back technique to emulate

an asynchronous preset or to emulate simultaneous preset and clear or

asynchronous load. However, this technique uses three additional LEs per

compiled. Registers that emulate simultaneous preset and load will enter

an unknown state upon power-up or when the chip-wide reset is asserted.

In addition to the two clear and preset modes, APEX 20KC devices

provide a chip-wide reset pin (DEV_CLRn) that resets all registers in the

device. Use of this pin is controlled through an option in the Quartus II

software that is set before compilation. The chip-wide reset overrides all

other control signals. Registers using an asynchronous preset are preset

when the chip-wide reset is asserted; this effect results from the inversion

technique used to implement the asynchronous preset.

FastTrack Interconnect

In the APEX 20KC architecture, connections between LEs, ESBs, and I/O

pins are provided by the FastTrack interconnect. The FastTrack

interconnect is a series of continuous horizontal and vertical routing

channels that traverse the device. This global routing structure provides

predictable performance, even in complex designs. In contrast, the

segmented routing in FPGAs requires switch matrices to connect a

variable number of routing paths, increasing the delays between logic

resources and reducing performance.

The FastTrack interconnect consists of row and column interconnect

channels that span the entire device. The row interconnect routes signals

throughout a row of MegaLAB structures; the column interconnect routes

signals throughout a column of MegaLAB structures. When using the row

and column interconnect, an LE, IOE, or ESB can drive any other LE, IOE,

or ESB in a device. See Figure 9.

APEX20KC bảng dữ liệu(PDF) 19 Page - Altera Corporation