APEX20KC datasheet(15/90 Pages) ALTERA

15 / 90 page

Altera Corporation

APEX 20KC Programmable Logic Device Data Sheet

Cascade Chain

With the cascade chain, the APEX 20KC architecture can implement

functions with a very wide fan-in. Adjacent LUTs can compute portions

of a function in parallel; the cascade chain serially connects the

intermediate values. The cascade chain can use a logical AND or logical OR

(via De Morgan’s inversion) to connect the outputs of adjacent LEs. Each

additional LE provides four more inputs to the effective width of a

function, with a short cascade delay. Cascade chain logic can be created

automatically by the Quartus II Compiler during design processing, or

manually by the designer during design entry.

Cascade chains longer than ten LEs are implemented automatically by

linking LABs together. For enhanced fitting, a long cascade chain skips

alternate LABs in a MegaLAB structure. A cascade chain longer than one

LAB skips either from an even-numbered LAB to the next even-numbered

LAB, or from an odd-numbered LAB to the next odd-numbered LAB. For

example, the last LE of the first LAB in the upper-left MegaLAB structure

carries to the first LE of the third LAB in the MegaLAB structure. Figure 7

shows how the cascade function can connect adjacent LEs to form

functions with a wide fan-in.

Figure 7. APEX 20KC Cascade Chain

LE1

LUT

LE2

LUT

d[3..0]

d[7..4]

d[(4

n – 1)..(4n – 4)]

d[3..0]

d[7..4]

LE1

LE2

LUT

AND Cascade Chain

OR Cascade Chain

d[(4

n – 1)..(4n – 4)]

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