APEX20KC datasheet(47/90 Pages) ALTERA

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Altera Corporation

APEX 20KC Programmable Logic Device Data Sheet

Clock Multiplication

The APEX 20KC ClockBoost circuit can multiply or divide clocks by a

programmable number. The clock can be multiplied by m/(n × k), where

m and k range from 2 to 160 and n ranges from 1 to 16. Clock multiplication

and division can be used for time-domain multiplexing and other

functions, which can reduce design LE requirements.

Clock Phase & Delay Adjustment

The APEX 20KC ClockShift feature allows the clock phase and delay to be

adjusted. The clock phase can be adjusted by 90° steps. The clock delay

can be adjusted to increase or decrease the clock delay by an arbitrary

amount, up to one clock period.

LVDS Support

All APEX 20KC devices support differential LVDS buffers on the input

and output clock signals that interface with external devices. This is

controlled in the Quartus II software by assigning the clock pins with an

LVDS I/O standard assignment.

Two high-speed PLLs are designed to support the LVDS interface. When

using LVDS, the I/O clock runs at a slower rate than the data transfer rate.

Thus, PLLs are used to multiply the I/O clock internally to capture the

LVDS data. For example, an I/O clock may run at 105 MHz to support

840 Mbps LVDS data transfer. In this example, the PLL multiplies the

incoming clock by eight to support the high-speed data transfer. You can

use PLLs in EP20K400C and larger devices for high-speed LVDS

interfacing.

Lock Signals

The APEX 20KC ClockLock circuitry supports individual LOCK signals.

The LOCK signal drives high when the ClockLock circuit has locked onto

the input clock. The LOCK signals are optional for each ClockLock circuit;

when not used, they are I/O pins.

APEX20KC bảng dữ liệu(PDF) 47 Page - Altera Corporation