APEX20KC datasheet(49/90 Pages) ALTERA

49 / 90 page

Altera Corporation

APEX 20KC Programmable Logic Device Data Sheet

Tables 11 and 12 summarize the ClockLock and ClockBoost parameters

for APEX 20KC devices.

Table 11. APEX 20KC ClockLock & ClockBoost Parameters

Note (1)

Symbol

Parameter

Condition

Min

Typ

Max

Unit

Input rise time

Input fall time

tINDUTY

Input duty cycle

tINJITTER

Input jitter peak-to-peak

% of input

period

tOUTJITTER

RMS jitter on ClockLock or

ClockBoost-generated clock

0.35

% of

output

period

tOUTDUTY

Duty cycle for ClockLock or

ClockBoost-generated clock

tLOCK (2), (3) Time required for ClockLock or

ClockBoost to acquire lock

µs

Table 12. APEX 20KC Clock Input & Output Parameters (Part 1 of 2)

Note (1)

Symbol

Parameter

I/O Standard

-7 Speed Grade

-8 Speed Grade

Units

Min

Max

Min

Max

fVCO (4)

Voltage controlled oscillator

operating range

200

500

200

500

MHz

fCLOCK0

Clock0 PLL output frequency

for internal use

1.5

335

1.5

200

MHz

fCLOCK1

Clock1 PLL output frequency

for internal use

335

200

MHz

fCLOCK0_EXT Output clock frequency for

external clock0 output

3.3-V LVTTL

(5)(5)

MHz

2.5-V LVTTL

(5)(5)

MHz

1.8-V LVTTL

(5)(5)

MHz

GTL+

(5)(5)

MHz

SSTL-2 Class I

(5)(5)

MHz

SSTL-2 Class II

(5)(5)

MHz

SSTL-3 Class I

(5)(5)

MHz

SSTL-3 Class II

(5)(5)

MHz

LVDS

(5)(5)

MHz

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