APEX20KC datasheet(68/90 Pages) ALTERA

68 / 90 page

Altera Corporation

APEX 20KC Programmable Logic Device Data Sheet

Figure 35. Synchronous Bidirectional Pin External Timing

Notes to Figure 35:

(1)

The output enable and input registers are LE registers in the LAB adjacent to the

bidirectional pin. Use the “Output Enable Routing = Single-Pin” option in the

Quartus II software to set the output enable register.

(2)

Use the “Decrease Input Delay to Internal Cells = OFF” option in the Quartus II

software to set the LAB-adjacent input register. This maintains a zero hold time for

LAB-adjacent registers while giving a fast, position-independent setup time. Set

“Decrease Input Delay to Internal Cells = ON” and move the input register farther

away from the bidirectional pin for a faster setup time with zero hold time. The

exact position where zero hold occurs with the minimum setup time varies with

device density and speed grade.

Tables 36 to 38 describes the fMAX timing parameters shown in Figure 32.

Table 39 describes the functional timing parameters.

PRN

CLRN

PRN

CLRN

OE Register

(1)

Bidirectional Pin

Dedicated

Clock

PRN

CLRN

Input Register

(1), (2)

XZBIDIR

ZXBIDIR

OUTCOBIDIR

INSUBIDIR

INHBIDIR

Output IOE Register

Table 36. APEX 20KC fMAX LE Timing Parameters

Symbol

Parameter

tSU

LE register setup time before clock

LE register hold time before clock

tCO

LE register clock-to-output delay

tLUT

LUT delay for data-in to data-out

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