APEX20KC datasheet(12/90 Pages) ALTERA

12 / 90 page

Altera Corporation

APEX 20KC Programmable Logic Device Data Sheet

Figure 5. APEX 20KC Logic Element

Each LE’s programmable register can be configured for D, T, JK, or SR

operation. The register’s clock and clear control signals can be driven by

global signals, general-purpose I/O pins, or any internal logic. For

combinatorial functions, the register is bypassed and the output of the

LUT drives the outputs of the LE.

Each LE has two outputs that drive the local, MegaLAB, or FastTrack

interconnect routing structure. Each output can be driven independently

by the LUT’s or register’s output. For example, the LUT can drive one

output while the register drives the other output. This feature, called

LUT can be used for unrelated functions. The LE can also drive out

registered and unregistered versions of the LUT output.

labclk1

labclk2

labclr1

labclr2

Carry-In

Clock & Clock

Enable Select

Carry-Out

Look-Up

Table

(LUT)

Carry

Chain

Cascade

Chain

Cascade-In

Cascade-Out

To FastTrack Interconnect,

MegaLAB Interconnect,

or Local Interconnect

To FastTrack Interconnect,

MegaLAB Interconnect,

or Local Interconnect

Programmable

PRN

CLRN

ENA

Packed

Chip-Wide

Reset

labclkena1

labclkena2

Synchronous

Load & Clear

Logic

LAB-wide

Synchronous

Load

LAB-wide

Synchronous

Clear

Asynchronous

Clear/Preset/

Load Logic

data1

data2

data3

data4

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