APEX20KC datasheet(48/90 Pages) ALTERA

48 / 90 page

Altera Corporation

APEX 20KC Programmable Logic Device Data Sheet

ClockLock & ClockBoost Timing Parameters

For the ClockLock and ClockBoost circuitry to function properly, the

incoming clock must meet certain requirements. If these specifications are

not met, the circuitry may not lock onto the incoming clock, which

generates an erroneous clock within the device. The clock generated by

the ClockLock and ClockBoost circuitry must also meet certain

specifications. If the incoming clock meets these requirements during

configuration, the APEX 20KC ClockLock and ClockBoost circuitry will

lock onto the clock during configuration. The circuit will be ready for use

immediately after configuration. In APEX 20KC devices, the clock input

standard is programmable, so the PLL cannot respond to the clock until

the device is configured. The PLL locks onto the input clock as soon as

configuration is complete. Figure 29 shows the incoming and generated

clock specifications.

For more information on ClockLock and ClockBoost circuitry,

see Application Note 115: Using the ClockLock and ClockBoost PLL

Features in APEX Devices.

Figure 29. Specifications for the Incoming & Generated Clocks

The tI parameter refers to the nominal input clock period; the tO parameter refers to the

nominal output clock period.

Note to Figure 29:

(1)

Rise and fall times are measured from 10% to 90%.

Input

Clock

ClockLock

Generated

Clock

f CLK1 f CLK2

f CLK4

t INDUTY

t I + t CLKDEV

t R

t F

t O

t I + t INCLKSTB

t O

t JITTER

tO + t JITTER

tOUTDUTY

(1)

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