APEX20KC datasheet(6/90 Pages) ALTERA

6 / 90 page

Altera Corporation

APEX 20KC Programmable Logic Device Data Sheet

All APEX 20KC devices are reconfigurable and are 100% tested prior to

shipment. As a result, test vectors do not have to be generated for fault-

coverage purposes. Instead, the designer can focus on simulation and

design verification. In addition, the designer does not need to manage

inventories of different application-specific integrated circuit (ASIC)

designs; APEX 20KC devices can be configured on the board for the

specific functionality required.

APEX 20KC devices are configured at system power-up with data stored

in an Altera serial configuration device or provided by a system

controller. Altera offers in-system programmability (ISP)-capable EPC16,

EPC8, EPC4, EPC2, and EPC1 configuration devices and one-time

programmable (OTP) EPC1 configuration devices, which configure

APEX 20KC devices via a serial data stream. Moreover, APEX 20KC

devices contain an optimized interface that permits microprocessors to

configure APEX 20KC devices serially or in parallel, and synchronously

or asynchronously. The interface also enables microprocessors to treat

APEX 20KC devices as memory and configure the device by writing to a

virtual memory location, making reconfiguration easy.

I/O standard support

1.8-V, 2.5-V, 3.3-V, 5.0-V I/O

3.3-V PCI and PCI-X

3.3-V AGP

CTT

GTL+

LVCMOS

LVTTL

True-LVDSTM and LVPECL data pins (in

EP20K400C and larger devices)

LVDS and LVPECL clock pins (in all devices)

LVDS and LVPECL data pins up to 156 Mbps

(in EP20K200C devices)

HSTL Class I

PCI-X

SSTL-2 Class I and II

SSTL-3 Class I and II

Memory support

CAM

Dual-port RAM

FIFO

RAM

ROM

Table 7. APEX 20KC Device Features (Part 2 of 2)

Feature

APEX 20KC Devices

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