APEX20KC datasheet(69/90 Pages) ALTERA

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Altera Corporation

APEX 20KC Programmable Logic Device Data Sheet

Table 37. APEX 20KC fMAX ESB Timing Parameters

Symbol

Parameter

tESBARC

ESB asynchronous read cycle time

tESBSRC

ESB synchronous read cycle time

tESBAWC

ESB asynchronous write cycle time

tESBSWC

ESB synchronous write cycle time

tESBWASU

ESB write address setup time with respect to WE

tESBWAH

ESB write address hold time with respect to WE

tESBWDSU

ESB data setup time with respect to WE

tESBWDH

ESB data hold time with respect to WE

tESBRASU

ESB read address setup time with respect to RE

tESBRAH

ESB read address hold time with respect to RE

tESBWESU

ESB WE setup time before clock when using input register

tESBDATASU

ESB data setup time before clock when using input register

tESBWADDRSU

ESB write address setup time before clock when using input registers

tESBRADDRSU

ESB read address setup time before clock when using input registers

tESBDATACO1

ESB clock-to-output delay when using output registers

tESBDATACO2

ESB clock-to-output delay without output registers

tESBDD

ESB data-in to data-out delay for RAM mode

tPD

ESB macrocell input to non-registered output

tPTERMSU

ESB macrocell register setup time before clock

tPTERMCO

ESB macrocell register clock-to-output delay

Table 38. APEX 20KC fMAX Routing Delays

Symbol

Parameter

tF1-4

Fan-out delay estimate using local interconnect

tF5-20

Fan-out delay estimate using MegaLab interconnect

tF20+

Fan-out delay estimate using FastTrack interconnect

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