ADC34RF72 datasheet(4/74 Pages) TI2

4 / 74 page

Table 4-1. Pin Functions (continued)

TYPE

(1)

DESCRIPTION

NAME

NO.

AVDDCLK12

T9, T10, U12

Clock power supply, 1.2V. Low noise LDO recommended

AVDD18

E9,H5,H13,J13,M6,M13,

N1,N6,N13,N17,P6,P13,

R6,R13,T1,T3,T4,T14,T15,

T17

Analog 1.8V supply. Low noise LDO recommended

AVDDCLK18

T8, T11

Clock power supply, 1.8V. Low noise LDO recommended

AVDDGPIO18

1.8V power supply for GPIO pins.

CLKN,

CLKP

U9,

U10

Differential clock input. Internal differential 100Ω termination and self bias to common mode

voltage of 0.7V. Must be AC coupled externally.

DVDD09

C8, D8, E8, F8,G8, H8, J8,

K8, K13, L6,L7, L8,

L9, L10, L11, L12, L13

Digital power supply, 0.9V. Switching DC/DC regulator is recommended.

GND

A1,A6,A9,A12,A17,B2,B16,

C10,D1,D10,D17,E10,F10,G5,

G9,G10,G13,H9,H10,

J6,J7,J9,J10,J11,J12,K6,

K7,K9,K10,K11,K12,M1,

M2,M5,M7,M9, M10,M12,

M16,M17,N2,N5,N9,N10,

N12,N16,P2,P5,P9,P10,

P12,P16,R2,R5,R7,R8,

R9,R10,R11,R12,R16,T2,

T5,T6,T13,T16,U1,U2,

U5,U8,U11,U13,U16,U17

Ground, 0V

GPIO1,

GPIO2,

GPIO3

K4,

L14,

J15

I/O

The GPIO pins can be assigned different functions using SPI writes. See Section 7.5.1.

GPIO8,

GPIO9,

GPIO10

L4,

J3,

K3,

I/O

GPIO12 to GPIO23

J2, K2, L2, C2,

D2, K16,L16, J17, K17,

L17, C16, D16

I/O

IN0N,

IN0P

R17,

P17

Differential analog input, ch 0. Internal programmable 50, 100 and 200Ω termination.

IN1N,

INIP

U14,

U15

Differential analog input, ch 1. Internal programmable 50, 100 and 200Ω termination.

IN2N,

IN2P

P1,

Differential analog input, ch 2. Internal programmable 50, 100 and 200Ω termination.

IN3N,

IN3P

U3,

Differential analog input, ch 3. Internal programmable 50, 100 and 200Ω termination.

JESDCLKN,

JESDCLKP

C9,

Differential JESD output clock. LVDS logic levels. Can be configured to serdes lane rate

divided by (8x k). By default this feature is powered down and pins can be left floating.

This output clock is derived directly from the internal SerDes PLL and does not provide

deterministic latency.

LVDSDCLK0N,

LVDSDCLK0P

F17,

E17

Differential LVDS bit clock output.

Not yet supported in software. Leave as 'No Connect'

LVDSDCLK1N,

LVDSDCLK1P

F1,

LVDSFCLK0N,

LVDSFCLK0P

H17,

G17

Differential LVDS frame clock output.

Not yet supported in software. Leave as 'No Connect'

LVDSFCLK1N,

LVDSFCLK1P

H1,

ADC32RF72

SBASAL2 – NOVEMBER 2025

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