HCS08 datasheet(152/198 Pages) NXP

152 / 198 page

Timer/Pulse-Width Modulator (S08TPMV2)

MC9S08QD4 Series MCU Data Sheet, Rev. 6

152

Freescale Semiconductor

If the associated port pin is not stable for at least two bus clock cycles before changing to input capture

mode, it is possible to get an unexpected indication of an edge trigger. Typically, a program would clear

status flags after changing channel configuration bits and before enabling channel interrupts or using the

status flags to avoid any unexpected behavior.

11.3.5

Timer Channel Value Registers (TPMxCnVH:TPMxCnVL)

These read/write registers contain the captured TPM counter value of the input capture function or the

output compare value for the output compare or PWM functions. The channel value registers are cleared

by reset.

In input capture mode, reading either byte (TPMxCnVH or TPMxCnVL) latches the contents of both bytes

into a buffer where they remain latched until the other byte is read. This latching mechanism also resets

(becomes unlatched) when the TPMxCnSC register is written.

Table 11-5. Mode, Edge, and Level Selection

CPWMS

MSnB:MSnA

ELSnB:ELSnA

Mode

Configuration

Pin not used for TPM channel; use as an external clock for the TPM or

revert to general-purpose I/O

Input capture

Capture on rising edge only

Capture on falling edge only

Capture on rising or falling edge

Output

compare

Software compare only

Toggle output on compare

Clear output on compare

Set output on compare

Edge-aligned

PWM

High-true pulses (clear output on compare)

Low-true pulses (set output on compare)

Center-aligned

PWM

High-true pulses (clear output on compare-up)

Low-true pulses (set output on compare-up)

321

Bit 15

Bit 8

Reset

000

Figure 11-9. Timer Channel Value Register High (TPMxCnVH)

321

Bit 7

Bit 0

Reset

000

Figure 11-10. Timer Channel Value Register Low (TPMxCnVL)

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