HCS08 datasheet(156/198 Pages) NXP

156 / 198 page

Timer/Pulse-Width Modulator (S08TPMV2)

MC9S08QD4 Series MCU Data Sheet, Rev. 6

156

Freescale Semiconductor

11.4.3

Center-Aligned PWM Mode

This type of PWM output uses the up-/down-counting mode of the timer counter (CPWMS = 1). The

output compare value in TPMxCnVH:TPMxCnVL determines the pulse width (duty cycle) of the PWM

signal and the period is determined by the value in TPMxMODH:TPMxMODL.

TPMxMODH:TPMxMODL must be kept in the range of 0x0001 to 0x7FFF because values outside this

range can produce ambiguous results. ELSnA will determine the polarity of the CPWM output.

pulse width = 2 x (TPMxCnVH:TPMxCnVL)

Eqn. 11-1

period = 2 x (TPMxMODH:TPMxMODL);

for TPMxMODH:TPMxMODL = 0x0001–0x7FFF

Eqn. 11-2

If the channel value register TPMxCnVH:TPMxCnVL is zero or negative (bit 15 set), the duty cycle will

be 0%. If TPMxCnVH:TPMxCnVL is a positive value (bit 15 clear) and is greater than the (nonzero)

modulus setting, the duty cycle will be 100% because the duty cycle compare will never occur. This

implies the usable range of periods set by the modulus register is 0x0001 through 0x7FFE (0x7FFF if

generation of 100% duty cycle is not necessary). This is not a significant limitation because the resulting

period is much longer than required for normal applications.

TPMxMODH:TPMxMODL = 0x0000 is a special case that must not be used with center-aligned PWM

mode. When CPWMS = 0, this case corresponds to the counter running free from 0x0000 through 0xFFFF,

but when CPWMS = 1 the counter needs a valid match to the modulus register somewhere other than at

0x0000 in order to change directions from up-counting to down-counting.

Figure 11-12 shows the output compare value in the TPM channel registers (multiplied by 2), which

determines the pulse width (duty cycle) of the CPWM signal. If ELSnA = 0, the compare match while

counting up forces the CPWM output signal low and a compare match while counting down forces the

output high. The counter counts up until it reaches the modulo setting in TPMxMODH:TPMxMODL, then

counts down until it reaches zero. This sets the period equal to two times TPMxMODH:TPMxMODL.

Figure 11-12. CPWM Period and Pulse Width (ELSnA = 0)

Center-aligned PWM outputs typically produce less noise than edge-aligned PWMs because fewer I/O pin

transitions are lined up at the same system clock edge. This type of PWM is also required for some types

of motor drives.

Because the HCS08 is a family of 8-bit MCUs, the settings in the timer channel registers are buffered to

ensure coherent 16-bit updates and to avoid unexpected PWM pulse widths. Writes to any of the registers,

TPMxMODH, TPMxMODL, TPMxCnVH, and TPMxCnVL, actually write to buffer registers. Values are

PERIOD

PULSE WIDTH

COUNT =

COUNT = 0

OUTPUT

COMPARE

(COUNT UP)

OUTPUT

COMPARE

(COUNT DOWN)

COUNT =

TPMxMODH:TPMx

TPM1C

TPMxMODH:TPMx

2 x

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