HCS08 datasheet(21/198 Pages) NXP

21 / 198 page

Chapter 2 External Signal Description

MC9S08QD4 Series MCU Data Sheet, Rev. 6

Freescale Semiconductor

2.2.2

Oscillator

Out of reset the MCU uses an internally generated clock provided by the internal clock source (ICS)

module. The internal frequency is nominally 16 MHz and the default ICS settings will provide for a 4 MHz

bus out of reset. For more information on the ICS, see the Internal Clock Source chapter.

2.2.3

Reset (Input Only)

After a power-on reset (POR) into user mode, the PTA5/TPM2CH0I/IRQ/RESET pin defaults to a

general-purpose input port pin, PTA5. Setting RSTPE in SOPT1 configures the pin to be the RESET input

pin. Once configured as RESET, the pin will remain RESET until the next POR. The RESET pin can be

used to reset the MCU from an external source when the pin is driven low. When enabled as the RESET

pin (RSTPE = 1), an internal pullup device is automatically enabled.

After a POR into active background mode, the PTA5/TPM2CH0I/IRQ/RESET pin defaults to the RESET

pin.

When TPM2 is configured for input capture, the pin will be the input capture pin TPM2CH0I.

NOTE

This pin does not contain a clamp diode to VDD and must not be driven

above VDD.

The voltage measured on the internally pulled up RESET pin may be as low

as VDD – 0.7 V. The internal gates connected to this pin are pulled to VDD.

2.2.4

Background / Mode Select (BKGD/MS)

During a power-on-reset (POR) or background debug force reset (see Section 5.8.3, “System Background

Debug Force Reset Register (SBDFR)” for more information), the PTA4/TPM2CH0O/BKGD/MS pin

functions as a mode select pin. Immediately after any reset, the pin functions as the background pin and

can be used for background debug communication. When enabled as the BKGD/MS pin (BKGDPE = 1),

an internal pullup device is automatically enabled.

The background debug communication function is enabled when BKGDPE in SOPT1 is set. BKGDPE is

set following any reset of the MCU and must be cleared to use the PTA4/TPM2CH0O/BKGD/MS pins

alternative pin functions.

If nothing is connected to this pin, the MCU will enter normal operating mode at the rising edge of the

internal reset after a POR or force BDC reset. If a debug system is connected to the 6-pin standard

background debug header, it can hold BKGD/MS low during a POR or immediately after issuing a

background debug force reset, which will force the MCU to active background mode.

The BKGD pin is used primarily for background debug controller (BDC) communications using a custom

protocol that uses 16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s BDC

clock could be as fast as the maximum bus clock rate, so there must never be any significant capacitance

connected to the BKGD/MS pin that could interfere with background serial communications.

HCS08 bảng dữ liệu(PDF) 21 Page - NXP Semiconductors