HCS08 datasheet(28/198 Pages) NXP

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Chapter 3 Modes of Operation

MC9S08QD4 Series MCU Data Sheet, Rev. 6

Freescale Semiconductor

After waking up from stop2, the PPDF bit in SPMSC2 is set. This flag may be used to direct user code to

go to a stop2 recovery routine. PPDF remains set and the I/O pin states remain latched until a logic 1 is

written to PPDACK in SPMSC2.

To maintain I/O state for pins that were configured as general-purpose I/O, the user must restore the

contents of the I/O port registers, which have been saved in RAM, to the port registers before writing to

the PPDACK bit. If the port registers are not restored from RAM before writing to PPDACK, then the

to their reset states.

For pins that were configured as peripheral I/O, the user must reconfigure the peripheral module that

interfaces to the pin before writing to the PPDACK bit. If the peripheral module is not enabled before

writing to PPDACK, the pins will be controlled by their associated port control registers when the I/O

latches are opened.

3.6.2

Stop3 Mode

Stop3 mode is entered by executing a STOP instruction under the conditions as shown in Table 3-1. The

states of all of the internal registers and logic, RAM contents, and I/O pin states are maintained.

Stop3 can be exited by asserting RESET, or by an interrupt from one of the following sources: the real-time

interrupt (RTI), LVD, ADC, IRQ, or the KBI.

If stop3 is exited by means of the RESET pin, then the MCU is reset and operation will resume after taking

the reset vector. Exit by means of one of the internal interrupt sources results in the MCU taking the

appropriate interrupt vector.

3.6.3

Active BDM Enabled in Stop Mode

Entry into the active background mode from run mode is enabled if the ENBDM bit in BDCSCR is set.

This register is described in Chapter 12, “Development Support,” of this data sheet. If ENBDM is set when

the CPU executes a STOP instruction, the system clocks to the background debug logic remain active

when the MCU enters stop mode so background debug communication is still possible. In addition, the

voltage regulator does not enter its low-power standby state but maintains full internal regulation. If the

user attempts to enter stop2 with ENBDM set, the MCU will instead enter stop3.

Most background commands are not available in stop mode. The memory-access-with-status commands

do not allow memory access, but they report an error indicating that the MCU is in either stop or wait

mode. The BACKGROUND command can be used to wake the MCU from stop and enter active

background mode if the ENBDM bit is set. After entering background debug mode, all background

commands are available. Table 3-2 summarizes the behavior of the MCU in stop when entry into the

background debug mode is enabled.

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