HCS08 datasheet(67/198 Pages) NXP

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MC9S08QD4 Series MCU Data Sheet, Rev. 6

Freescale Semiconductor

Chapter 6

Parallel Input/Output Control

This section explains software controls related to parallel input/output (I/O) and pin control. The

MC9S08QD4 series has one parallel I/O port which include a total of 4 I/O pins, one output-only pin, and

one input-only pin. See Section Chapter 2, “External Signal Description,” for more information about pin

assignments and external hardware considerations of these pins.

All of these I/O pins are shared with on-chip peripheral functions as shown in Table 2-1. The peripheral

modules have priority over the I/Os so that when a peripheral is enabled, the I/O functions associated with

the shared pins are disabled. After reset, the shared peripheral functions are disabled so that the pins are

controlled by the I/O. All of the I/Os are configured as inputs (PTxDDn = 0) with pullup devices disabled

(PTxPEn = 0), except for output-only pin PTA4 which defaults to BKGD/MS pin.

NOTE

Not all general-purpose I/O pins are available on all packages. To avoid

extra current drain from floating input pins, the user’s reset initialization

routine in the application program must either enable on-chip pullup devices

or change the direction of unconnected pins to outputs so the pins do not

float.

6.1

Port Data and Data Direction

Reading and writing of parallel I/Os is performed through the port data registers. The direction, either input

or output, is controlled through the port data direction registers. The parallel I/O port function for an

individual pin is illustrated in the block diagram shown in Figure 6-1.

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