HCS08 datasheet(70/198 Pages) NXP

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Chapter 6 Parallel Input/Output Control

MC9S08QD4 Series MCU Data Sheet, Rev. 6

Freescale Semiconductor

6.4.1.2

Port A Data Direction (PTADD)

6.4.2

Port A Control Registers

The pins associated with port A are controlled by the registers in this section. These registers control the

pin pullup, slew rate and drive strength of the Port A pins independent of the parallel I/O register.

Table 6-1. PTAD Register Field Descriptions

Field

Description

5:0

PTAD[5:0]

Port A Data Register Bits — For port A pins that are inputs, reads return the logic level on the pin. For port A

pins that are configured as outputs, reads return the last value written to this register.

Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level is

driven out the corresponding MCU pin.

Reset forces PTAD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures

all port pins as high-impedance inputs with pullups disabled.

321

PTADD51

PTADD42

PTADD3

PTADD2

PTADD1

PTADD0

Reset:

000

1 PTADD5 has no effect on the input-only PTA5 pin. Read this bit is always equal to zero.

2 PTADD4 has no effect on the output-only PTA4 pin.

Figure 6-3. Port A Data Direction Register (PTADD)

Table 6-2. PTADD Register Field Descriptions

Field

Description

5:0

PTADD[5:0]

Data Direction for Port A Bits — These read/write bits control the direction of port A pins and what is read for

PTAD reads.

0 Input (output driver disabled) and reads return the pin value.

1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn.

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