HCS08 datasheet(69/198 Pages) NXP

69 / 198 page

Chapter 6 Parallel Input/Output Control

MC9S08QD4 Series MCU Data Sheet, Rev. 6

Freescale Semiconductor

•

In stop1 mode, all internal registers including parallel I/O control and data registers are powered

off. Each of the pins assumes its default reset state (output buffer and internal pullup disabled).

Upon exit from stop1, all pins must be re-configured the same as if the MCU had been reset.

•

Stop2 mode is a partial power-down mode, whereby latches maintain the pin state as before the

STOP instruction was executed. CPU register status and the state of I/O registers must be saved in

RAM before the STOP instruction is executed to place the MCU in stop2 mode. Upon recovery

from stop2 mode, before accessing any I/O, the user must examine the state of the PPDF bit in the

SPMSC2 register. If the PPDF bit is 0, I/O must be initialized as if a power on reset had occurred.

If the PPDF bit is 1, I/O data previously stored in RAM, before the STOP instruction was executed,

peripherals previously enabled will require being initialized and restored to their pre-stop

condition. The user must then write a 1 to the PPDACK bit in the SPMSC2 register. Access of pins

is now permitted again in the user’s application program.

•

In stop3 mode, all pin states are maintained because internal logic stays powered up. Upon

recovery, all pin functions are the same as before entering stop3.

6.4

Parallel I/O Registers

6.4.1

Port A Registers

This section provides information about the registers associated with the parallel I/O ports.

Refer to tables in Chapter 4, “Memory Map and Register Definition,” for the absolute address assignments

for all parallel I/O. This section refers to registers and control bits only by their names. A Freescale

Semiconductor-provided equate or header file normally is used to translate these names into the

appropriate absolute addresses.

6.4.1.1

Port A Data (PTAD)

321

PTAD51

PTAD42

PTAD3

PTAD2

PTAD1

PTAD0

Reset:

000

1 Reads of bit PTAD5 always return the pin value of PTA5, regardless of the value stored in bit PTADD5.

2 Reads of bit PTAD4 always return the contents of PTAD4, regardless of the value stored in bit PTADD4.

Figure 6-2. Port A Data Register (PTAD)

HCS08 bảng dữ liệu(PDF) 69 Page - NXP Semiconductors

HCS08 bảng dữ liệu(HTML) 69 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL