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HCS08 bảng dữ liệu(PDF) 33 Page - NXP Semiconductors |
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HCS08 bảng dữ liệu(HTML) 33 Page - NXP Semiconductors |
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33 / 198 page  Chapter 4 Memory Map and Register Definition MC9S08QD4 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor 33 4.3 Register Addresses and Bit Assignments The registers in the MC9S08QD4 series are divided into these groups: • Direct-page registers are located in the first 96 locations in the memory map; these are accessible with efficient direct addressing mode instructions. • High-page registers are used much less often, so they are located above 0x1800 in the memory map. This leaves more room in the direct page for more frequently used registers and RAM. • The nonvolatile register area consists of a block of 16 locations in flash memory at 0xFFB0–0xFFBF. Nonvolatile register locations include: — NVPROT and NVOPT are loaded into working registers at reset — An 8-byte backdoor comparison key that optionally allows a user to gain controlled access to secure memory Because the nonvolatile register locations are flash memory, they must be erased and programmed like other flash memory locations. Direct-page registers can be accessed with efficient direct addressing mode instructions. Bit manipulation instructions can be used to access any bit in any direct-page register. Table 4-2 is a summary of all user-accessible direct-page registers and control bits. The direct page registers in Table 4-2 can use the more efficient direct addressing mode that requires only the lower byte of the address. Because of this, the lower byte of the address in column one is shown in bold text. In Table 4-3 and Table 4-4, the whole address in column one is shown in bold. In Table 4-2, Table 4-3, and Table 4-4, the register names in column two are shown in bold to set them apart from the bit names to the right. Cells that are not associated with named bits are shaded. A shaded cell with a 0 indicates this unused bit always reads as a 0. Shaded cells with dashes indicate unused or reserved bit locations that could read as 1s or 0s. Table 4-2. Direct-Page Register Summary Address Register Name Bit 7 654321 Bit 0 0x0000 PTAD 0 0 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0 0x0001 PTADD 0 0 PTADD5 PTADD4 PTADD3 PTADD2 PTADD1 PTADD0 0x0002– 0x000B Reserved — — — — — — — — — — — — — — — — 0x000C KBISC 0 0 0 0 KBF KBACK KBIE KBIMOD 0x000D KBIPE KBIPE7 KBIPE6 KBIPE5 KBIPE4 KBIPE3 KBIPE2 KBIPE1 KBIPE0 0x000E KBIES KBEDG7 KBEDG6 KBEDG5 KBEDG4 KBEDG3 KBEDG2 KBEDG1 KBEDG0 0x000F IRQSC 0 IRQPDD IRQEDG IRQPE IRQF IRQACK IRQIE IRQMOD 0x0010 ADCSC1 COCO AIEN ADCO ADCH 0x0011 ADCSC2 ADACT ADTRG ACFE ACFGT — — — — 0x0012 ADCRH 0 0 0 0 0 0 ADR9 ADR8 0x0013 ADCRL ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 0x0014 ADCCVH 0 0 0 0 0 0 ADCV9 ADCV8 0x0015 ADCCVL ADCV7 ADCV6 ADCV5 ADCV4 ADCV3 ADCV2 ADCV1 ADCV0 0x0016 ADCCFG ADLPC ADIV ADLSMP MODE ADICLK |
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