HCS08 datasheet(154/198 Pages) NXP

154 / 198 page

Timer/Pulse-Width Modulator (S08TPMV2)

MC9S08QD4 Series MCU Data Sheet, Rev. 6

154

Freescale Semiconductor

When center-aligned PWM operation is specified, the counter counts upward from 0x0000 through its

terminal count and then counts downward to 0x0000 where it returns to up-counting. Both 0x0000 and the

terminal count value (value in TPMxMODH:TPMxMODL) are normal length counts (one timer clock

period long).

An interrupt flag and enable are associated with the main 16-bit counter. The timer overflow flag (TOF) is

a software-accessible indication that the timer counter has overflowed. The enable signal selects between

software polling (TOIE = 0) where no hardware interrupt is generated, or interrupt-driven operation

(TOIE = 1) where a static hardware interrupt is automatically generated whenever the TOF flag is 1.

The conditions that cause TOF to become set depend on the counting mode (up or up/down). In

up-counting mode, the main 16-bit counter counts from 0x0000 through 0xFFFF and overflows to 0x0000

on the next counting clock. TOF becomes set at the transition from 0xFFFF to 0x0000. When a modulus

limit is set, TOF becomes set at the transition from the value set in the modulus register to 0x0000. When

the main 16-bit counter is operating in up-/down-counting mode, the TOF flag gets set as the counter

changes direction at the transition from the value set in the modulus register and the next lower count

value. This corresponds to the end of a PWM period. (The 0x0000 count value corresponds to the center

of a period.)

Because the HCS08 MCU is an 8-bit architecture, a coherency mechanism is built into the timer counter

for read operations. Whenever either byte of the counter is read (TPMxCNTH or TPMxCNTL), both bytes

are captured into a buffer so when the other byte is read, the value will represent the other byte of the count

at the time the first byte was read. The counter continues to count normally, but no new value can be read

from either byte until both bytes of the old count have been read.

The main timer counter can be reset manually at any time by writing any value to either byte of the timer

count TPMxCNTH or TPMxCNTL. Resetting the counter in this manner also resets the coherency

mechanism in case only one byte of the counter was read before resetting the count.

11.4.2

Channel Mode Selection

Provided CPWMS = 0 (center-aligned PWM operation is not specified), the MSnB and MSnA control bits

in the channel n status and control registers determine the basic mode of operation for the corresponding

channel. Choices include input capture, output compare, and buffered edge-aligned PWM.

11.4.2.1

Input Capture Mode

With the input capture function, the TPM can capture the time at which an external event occurs. When an

active edge occurs on the pin of an input capture channel, the TPM latches the contents of the TPM counter

into the channel value registers (TPMxCnVH:TPMxCnVL). Rising edges, falling edges, or any edge may

be chosen as the active edge that triggers an input capture.

When either byte of the 16-bit capture register is read, both bytes are latched into a buffer to support

coherent 16-bit accesses regardless of order. The coherency sequence can be manually reset by writing to

the channel status/control register (TPMxCnSC).

An input capture event sets a flag bit (CHnF) that can optionally generate a CPU interrupt request.

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