HCS08 datasheet(151/198 Pages) NXP

151 / 198 page

Timer/Pulse-Width Modulator (S08TPMV2)

MC9S08QD4 Series MCU Data Sheet, Rev. 6

Freescale Semiconductor

151

11.3.4

Timer Channel n Status and Control Register (TPMxCnSC)

TPMxCnSC contains the channel interrupt status flag and control bits that are used to configure the

interrupt enable, channel configuration, and pin function.

321

CHnF

CHnIE

MSnB

MSnA

ELSnB

ELSnA

Reset

000

= Unimplemented or Reserved

Figure 11-8. Timer Channel n Status and Control Register (TPMxCnSC)

Table 11-4. TPMxCnSC Register Field Descriptions

Field

Description

CHnF

Channel n Flag — When channel n is configured for input capture, this flag bit is set when an active edge occurs

on the channel n pin. When channel n is an output compare or edge-aligned PWM channel, CHnF is set when

the value in the TPM counter registers matches the value in the TPM channel n value registers. This flag is

seldom used with center-aligned PWMs because it is set every time the counter matches the channel value

A corresponding interrupt is requested when CHnF is set and interrupts are enabled (CHnIE = 1). Clear CHnF

by reading TPMxCnSC while CHnF is set and then writing a 0 to CHnF. If another interrupt request occurs before

the clearing sequence is complete, the sequence is reset so CHnF would remain set after the clear sequence

was completed for the earlier CHnF. This is done so a CHnF interrupt request cannot be lost by clearing a

previous CHnF. Reset clears CHnF. Writing a 1 to CHnF has no effect.

0 No input capture or output compare event occurred on channel n

1 Input capture or output compare event occurred on channel n

CHnIE

Channel n Interrupt Enable — This read/write bit enables interrupts from channel n. Reset clears CHnIE.

0 Channel n interrupt requests disabled (use software polling)

1 Channel n interrupt requests enabled

MSnB

Mode Select B for TPM Channel n — When CPWMS = 0, MSnB = 1 configures TPM channel n for

edge-aligned PWM mode. For a summary of channel mode and setup controls, refer to Table 11-5.

MSnA

Mode Select A for TPM Channel n — When CPWMS = 0 and MSnB = 0, MSnA configures TPM channel n for

input capture mode or output compare mode. Refer to Table 11-5 for a summary of channel mode and setup

controls.

3:2

ELSn[B:A]

Edge/Level Select Bits — Depending on the operating mode for the timer channel as set by

CPWMS:MSnB:MSnA and shown in Table 11-5, these bits select the polarity of the input edge that triggers an

input capture event, select the level that will be driven in response to an output compare match, or select the

polarity of the PWM output.

Setting ELSnB:ELSnA to 0:0 configures the related timer pin as a general-purpose I/O pin unrelated to any timer

channel functions. This function is typically used to temporarily disable an input capture channel or to make the

timer pin available as a general-purpose I/O pin when the associated timer channel is set up as a software timer

that does not require the use of a pin.

HCS08 bảng dữ liệu(PDF) 151 Page - NXP Semiconductors

HCS08 bảng dữ liệu(HTML) 151 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL