HCS08 datasheet(150/198 Pages) NXP

150 / 198 page

Timer/Pulse-Width Modulator (S08TPMV2)

MC9S08QD4 Series MCU Data Sheet, Rev. 6

150

Freescale Semiconductor

When background mode is active, the timer counter and the coherency mechanism are frozen such that the

buffer latches remain in the state they were in when the background mode became active even if one or

both bytes of the counter are read while background mode is active.

11.3.3

Timer Counter Modulo Registers (TPMxMODH:TPMxMODL)

The read/write TPM modulo registers contain the modulo value for the TPM counter. After the TPM

counter reaches the modulo value, the TPM counter resumes counting from 0x0000 at the next clock

(CPWMS = 0) or starts counting down (CPWMS = 1), and the overflow flag (TOF) becomes set. Writing

to TPMxMODH or TPMxMODL inhibits TOF and overflow interrupts until the other byte is written.

Reset sets the TPM counter modulo registers to 0x0000, which results in a free-running timer counter

(modulo disabled).

It is good practice to wait for an overflow interrupt so both bytes of the modulo register can be written well

before a new overflow. An alternative approach is to reset the TPM counter before writing to the TPM

modulo registers to avoid confusion about when the first counter overflow will occur.

321

Bit 7

Bit 0

Any write to TPMxCNTL clears the 16-bit counter.

Reset

000

Figure 11-5. Timer Counter Register Low (TPMxCNTL)

321

Bit 15

Bit 8

Reset

000

Figure 11-6. Timer Counter Modulo Register High (TPMxMODH)

321

Bit 7

Bit 0

Reset

000

Figure 11-7. Timer Counter Modulo Register Low (TPMxMODL)

HCS08 bảng dữ liệu(PDF) 150 Page - NXP Semiconductors