HCS08 datasheet(149/198 Pages) NXP

149 / 198 page

Timer/Pulse-Width Modulator (S08TPMV2)

MC9S08QD4 Series MCU Data Sheet, Rev. 6

Freescale Semiconductor

149

11.3.2

Timer Counter Registers (TPMxCNTH:TPMxCNTL)

The two read-only TPM counter registers contain the high and low bytes of the value in the TPM counter.

Reading either byte (TPMxCNTH or TPMxCNTL) latches the contents of both bytes into a buffer where

they remain latched until the other byte is read. This allows coherent 16-bit reads in either order. The

coherency mechanism is automatically restarted by an MCU reset, a write of any value to TPMxCNTH or

TPMxCNTL, or any write to the timer status/control register (TPMxSC).

Reset clears the TPM counter registers.

Table 11-2. TPM Clock Source Selection

CLKSB:CLKSA

TPM Clock Source to Prescaler Input

0:0

No clock selected (TPMx disabled)

0:1

Bus rate clock (BUSCLK)

1:0

Fixed system clock (XCLK)

1:1

External source (TPMxCLK)1,2

1 The maximum frequency that is allowed as an external clock is one-fourth of the bus

frequency.

2 If the external clock input is shared with channel n and is selected as the TPM clock source,

the corresponding ELSnB:ELSnA control bits must be set to 0:0 so channel n does not try to

use the same pin for a conflicting function.

Table 11-3. Prescale Divisor Selection

PS2:PS1:PS0

TPM Clock Source Divided-By

0:0:0

0:0:1

0:1:0

0:1:1

1:0:0

1:0:1

1:1:0

1:1:1

128

321

Bit 15

Bit 8

Any write to TPMxCNTH clears the 16-bit counter.

Reset

000

Figure 11-4. Timer Counter Register High (TPMxCNTH)

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