CYT4DNJBJS datasheet(174/209 Pages) INFINEON

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Datasheet

174

002-24601 Rev. *I

2023-02-14

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Electrical specifications

Notes

• One of the modes (“CMOS”, “JEDEC” or “JEDEC with slave DS”) needs to be selected depending on the requirements of the actual

memory.

• Some parameters may be available and listed separately for the individual modes. The corresponding mode will be mentioned in the

parameter description.

• Parameters without explicit mode description (e.g. tOSU)are applicable for all modes butthe voltagereferencelevel asperthe tablestill

applies.

• Ifaparameterexistsfor“JEDEC”butnotfor“JEDECwithslaveDS”,the“JEDEC”parameteralsoappliesto“JEDECwithslaveDS”(e.g.tRQ).

Figure 26-2

xSPI master data input timing reference level (JEDEC)

Table 26-36

xSPI (JEDEC JESD251) Tap/DLL setting requirement

Feature

xSPI333

xSPI266

xSPI200

Tx (MDL) Rx (SDL) Tx (MDL) Rx (SDL) Tx (MDL) Rx (SDL)

Delay Tap Setting for SMIF0

(Tx (MDL): SMIF_CORE_CTL2:MDL_TAP_SEL

Rx (SDL): SMIF_CORE_DEVICE_RX_CAPTURE_CONFIG:NEG_SDL_TAP_SEL /

POS_SDL_TAP_SEL)

Delay Tap Setting for SMIF1

(Tx (MDL): SMIF_CORE_CTL2:MDL_TAP_SEL

Rx (SDL): SMIF_CORE_DEVICE_RX_CAPTURE_CONFIG:NEG_SDL_TAP_SEL /

POS_SDL_TAP_SEL)

DLL Speed Mode (SMIF_CORE_CTL2:DLL_SPEED_MODE)

Table 26-37

Input, output supported voltage reference levels

Signal

Supported modes for voltage reference levels

CMOS

JEDEC

JEDEC with slave DS

Clock

VT = (50% × VDDIO_SMIF)

RWDS (output)

VT = (50% × VDDIO_SMIF)VOH/VOL=70%/30%×VDDIO_SMIF

DQ[7:0] (output)

VT = (50% × VDDIO_SMIF)VOH/VOL = 70% / 30% × VDDIO_SMIF

RWDS (input)

VT = (50% × VDDIO_SMIF)

DQ[7:0] (input)

VT = (50% × VDDIO_SMIF)VIH/VIL = 70% / 30% × VDDIO_SMIF

tCK

VDDIO_SMIF

VSS

Data

Strobe

Data

Input

VSS

tDSMPW

VIH

VIL

tRQ

tRQH

Data Stable

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