CYT4DNJBJS datasheet(176/209 Pages) INFINEON

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Datasheet

176

002-24601 Rev. *I

2023-02-14

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Electrical specifications

Table 26-38

SMIF specifications

Spec ID

Parameter

Description

Min

Typ

Max

Units

Details/

conditions

Standard SPI SDR

Recommended configuration:

HSIO_ENH/1.8V I/O: CFG_OUT2/DS_TRIM<2:0 = 0b110, CFG_SLEW_EXT/SLEW<0:0> = 0b0

SMIF_CORE_CTL2:TX_SDR_EXTRA_SETUP = 1

DLL Tap settings for SMIF0/1:

SMIF_CORE_CTL2:MDL_TAP_SEL = 12

Following DLL Tap settings have to be used if DLP is not used:

SMIF_CORE_DEVICE_RX_CAPTURE_CONFIG:NEG_SDL_TAP_SEL / POS_SDL_TAP_SEL = 8

All timings aligned with respect to VT = (50% × VDDIO_SMIF).

SID1600[87] tCK

Interface clock period

–

100

15-pF output loads,

at 1.8 V

160 MHz ≤ fDLL≤ 333MHz

SID1601

tCKPW

Clock pulse width

0.45 ×

tCK

–

0.55 ×

tCK

15-pF output loads

SID1602_HS tCSS

CS# active setup to CK

(fCK > 50 MHz)

–

15-pF output loads,

fCK > 50 MHz

Guaranteed by

design

SID1602_LS tCSS

CS# active setup to CK

(fCK ≤ 50 MHz)

–

15-pF output loads,

fCK ≤ 50 MHz

Guaranteed by

design

SID1603

tCSH0

CS# active hold to CK

(mode 0)

–

15-pF output loads

Guaranteed by

design

SID1604

tCSH3

CS# active hold to CK

(mode 3)

–

15-pF output loads

Guaranteed by

design

SID1605[88] tOSU

Outputsetup timeof DQ[7:0] to

CK high (fCK = 166 MHz)

2.1

–

15-pF output loads,

using 1.8 V

SID1606[89] tOH

Output hold time of DQ[7:0] to

CK high (fCK = 166 MHz)

2.1

–

15-pF output loads,

using 1.8 V

SID1607

tIN_V

CK low to DQ[7:0] input valid

time

–

6.7

Only valid in DLP

mode

SID1607B

tISU

DQ[7:0] input setup time

tCK/4

– 0.25

–

Only valid in non-DLP

mode

160MHz≤fDLL≤333MHz

80 MHz ≤ fCK ≤ 166 MHz

SMIF0_COREx-

_CTL2.CLKOUT_DIV =

0b00 (divide by 2)

Reference CK edge: Fall

(pos edge capture

mode)

Note

87.Ensure to explicitly configure PLL#400 in Integer mode with "SSCG = OFF", "Fractional = OFF".

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