CYT4DNJBJS datasheet(173/209 Pages) INFINEON

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Datasheet

173

002-24601 Rev. *I

2023-02-14

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Electrical specifications

26.14

Serial memory interface specifications

Table 26-35

xSPI specifications

Spec ID

Parameter

Description

Min

Max

Min

Max

Min

Max

Units

xSPI (JEDEC JESD251)

xSPI333

xSPI266

xSPI200

Recommended I/O configuration:

xSPI333: HSIO_ENH/1.8 V: CFG_OUT2/DS_TRIM<2:0> = 0b110, CFG_SLEW_EXT/SLEW<0:0> = 0b0 (dual slave [7.5 pF < load  15 pF])

xSPI333: HSIO_ENH/1.8 V: CFG_OUT2/DS_TRIM<2:0> = 0b100, CFG_SLEW_EXT/SLEW<0:0> = 0b0 (single slave [load  7.5 pF])

xSPI266: HSIO_ENH/1.8 V: CFG_OUT2/DS_TRIM<2:0> = 0b110, CFG_SLEW_EXT/SLEW<0:0> = 0b0 (dual slave [7.5 pF < load  15 pF])

xSPI266: HSIO_ENH/1.8 V: CFG_OUT2/DS_TRIM<2:0> = 0b100, CFG_SLEW_EXT/SLEW<0:0> = 0b0 (single slave [load  7.5 pF])

xSPI200: HSIO_ENH/1.8 V: CFG_OUT2/DS_TRIM<2:0> = 0b110, CFG_SLEW_EXT/SLEW<0:0> = 0b0 (dual slave [7.5 pF < load  15 pF])

xSPI200: HSIO_ENH/1.8 V: CFG_OUT2/DS_TRIM<2:0> = 0b100, CFG_SLEW_EXT/SLEW<0:0> = 0b0 (single slave [load  7.5 pF])

SID1500

tCK

Interface clock period (JEDEC)

–

7.5

–

SID1500DS

tCK

Interface clock period (JEDEC with slave DS)

6.8

–

7.5

–

SID1500CM

tCK

Interface clock period (CMOS)

–

7.5

–

SID1501

tCKDCD

Allowable clock distortion[86]

–

0.05 × tCK

–

0.05 × tCK

–

0.05 × tCK

SID1502

tCKMPW

Minimum clock pulse width (JEDEC)

2.7

–

3.375

–

4.5

–

SID1502DS

tCKMPW

Minimum clock pulse width (JEDEC with

slave DS)

3.06

–

3.375

–

4.5

–

SID1502CM

tCKMPW

Minimum clock pulse width (CMOS)

2.7

–

3.375

–

4.5

–

SID1503

OUT_SR

Output slew rate with respect to VOH/VOL

0.94

–

0.75

–

0.56

–

V/ns

SID1504

tOSU

Output setup time of DS and I/O[7:0] to CK

0.7

–

0.9

–

1.1

–

SID1505

tOH

Output hold time of DS and I/O[7:0] to CK

0.7

–

0.9

–

1.1

–

SID1506

IN_SR

Input slew rate with respect to VIH/VIL

0.94

–

0.75

–

0.56

–

V/ns

SID1507

tDSMPW

Input min pulse width of DS (JEDEC)

2.46

–

3.075

–

4.1

–

SID1507CM

tDSMPW

Input min pulse width of DS (CMOS)

2.46

–

3.075

–

4.1

–

SID1508

tRQ

Input DS to I/O[7:0] valid time (JEDEC)

–

0.54

–

0.675

–

0.9

SID1508CM

tRQ

Input DS to I/O[7:0] valid time (CMOS)

–

0.51

–

0.675

–

0.9

SID1509

tRQH

Input I/O[7:0] invalid to DS time (JEDEC)

–

0.54

–

0.675

–

0.9

SID1509CM

tRQH

Input I/O[7:0] invalid to DS time (CMOS)

–

0.51

–

0.675

–

0.9

SID1511

tCKLCSL

CK LOW to CS LOW

4.8

–6

–8

–

SID1512

tCSLCKH

CS LOW to CK HIGH

4.8

–

6–

8–

SID1513

tCKLCSH

CK LOW to CS HIGH

4.8

–

6–

8–

SID1514

tCSHCKH

CS HIGH to CK HIGH

4.8

–

SID1515

tDSLCSH

DS LOW to CS HIGH

4.8

–

6–

8–

SID1516

tCSHDST

CS HIGH to DS High-Z

–

7.5

–

SID1517

tCSLDSL

CS LOW to DS LOW

–0

–

SID1518

tDSTCSL

DS High-Z to CS LOW

–0

–

Notes

86. PLL#400 with SSCG = 0, fractional divider = off.

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