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CYT4DNJBJS bảng dữ liệu(PDF) 180 Page - Infineon Technologies AG |
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CYT4DNJBJS bảng dữ liệu(HTML) 180 Page - Infineon Technologies AG |
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180 / 209 page  Datasheet 180 002-24601 Rev. *I 2023-02-14 TRAVEO™ T2G 32-bit Automotive MCU Based on Arm® Cortex®-M7 dual Electrical specifications 26.15 Graphics subsystem specifications Table 26-39 Graphics specifications Spec ID Parameter Description Min Typ Max Units Details/Conditions Display Output - TTL Mode Recommended I/O configuration: HSIO_STD: CFG_OUT/DRIVE_SEL<1:0> = 0b01 HSIO_STDLN: CFG_DRIVE_EXT<1:0>/DRIVE_SEL_EXT<2:0> = 0b010, CFG_SLEW_EXT/SLEW<0:0> = 0b0 SID866A tDC1CYC Clock Cycle 12.5 – – ns TTL_DSP1_CLOCK, CL = 15 pF SID873A tDC1CKPW Clock pulse width 0.40 × tDC1CYC – 0.60 × tDC1CYC ns TTL_DSP1_CLOCK pulse width, CL = 15 pF SID868A tDC1S Data/Control output to TTL_D- SP1_CLOCK time 4 – – ns TTL_DSP1_DATA_A0[11-0] TTL_DSP1_DATA_A1[11-0] TTL_DSP1_CONTROL[11-0] (TCON for FPD-Link) CL = 15 pF SID869A tDC1H TTL_DSP1_CLOCK to Data/Control valid time 2.5 – – ns TTL_DSP1_DATA_A0[11-0] TTL_DSP1_DATA_A1[11-0] TTL_DSP1_CONTROL[11-0] (TCON for FPD-Link) CL = 15 pF SID890 tDSP0_CON- TROL_SKEW TTL_DSP0_CONTROL skew – – 4 ns Skew between signals TTL_DSP0_CONTROL[11-3] CL = 15 pF Display Capture Recommended I/O configuration: CFG_IN_AUTOLVL/VTRIP_SEL<0:0>= 0b0, CFG_IN/VTRIP_SEL<0:0> = 0b0 SID875 tCAP0CYC Display capture Clock Cycle 12.5 – – ns TTL_CAP0_CLK (HSIO) SID876 tCAP0SU Display capture data setup time 1.9 – – ns TTL_CAP0_DATA[35-0] (HSIO) SID877 tCAP0HD Display capture data hold time 2.7 – – ns TTL_CAP0_DATA[35-0] (HSIO) FPD-Link SID880 IVDDA Total analog supply current in TX mode – – 30 mA SID881 IVDDPLL Total PLL supply current in TX mode – – 4 mA SID881B IVDDHA Total I/O (LVDS driver) supply current in TX mode – – 91 mA SID882 IVDDA_DPIX Total analog supply current in Dual-Pixel mode – – 60 mA SID883 IVDDPLL_DPIX Total PLL supply current in Dual-Pixel mode – – 4 mA SID883B IVDDHA_DPIX Total I/O (LVDS driver) supply current in Dual-Pixel mode – – 182 mA SID884 IVDDA_PD Total analog supply current in Power-Down mode – 4 300 µA Typ: TA = 25°C, VDDA_FPD = 1.15 V, process typ (TT) Max: TA = 105°C, VDDA_FPD = 1.21 V, process worst (FF) SID884_1 IVDDA_PD_1 Total analog supply current in Power-Down mode (room temp) – – 5 µA Max: TA = 25°C, VDDA_FPD = 1.15 V (max VREG), process worst (FF) SID884_2 IVDDA_PD_2 Total analog supply current in Power-Down mode – – 40 µA Max: TA = 85°C, VDDA_FPD = 1.15 V (max VREG), process worst (FF) SID885 IVDDPLL_PD Total PLL supply current in Power-Down mode – 3 200 µA Typ: TA = 25°C, VDDPLL_FPD = 1.15 V, process typ (TT) Max: TA = 105°C, VDDPLL_FPD = 1.21 V, process worst (FF) |
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