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CYT4DNJBJS bảng dữ liệu(PDF) 182 Page - Infineon Technologies AG |
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CYT4DNJBJS bảng dữ liệu(HTML) 182 Page - Infineon Technologies AG |
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182 / 209 page  Datasheet 182 002-24601 Rev. *I 2023-02-14 TRAVEO™ T2G 32-bit Automotive MCU Based on Arm® Cortex®-M7 dual Electrical specifications SID916 TPPos3 Transmit Pulse Position Offset 3 3T / 7 – TPPos0 3T / 7 3T / 7 + TPPos0 ns SID917 TPPos4 Transmit Pulse Position Offset 4 4T / 7 – TPPos0 4T / 7 4T / 7 + TPPos0 ns SID918 TPPos5 Transmit Pulse Position Offset 5 5T / 7 – TPPos0 5T / 7 5T / 7 + TPPos0 ns SID919 TPPos6 Transmit Pulse Position Offset 6 6T / 7 – TPPos0 6T / 7 6T / 7 + TPPos0 ns SID920 tLLHT Differential driver rise time – – 390 ps SID921 tLHLT Differential driver fall time – – 390 ps SID922 tRF_MATCH Lane-to-lane rise/fall delta – – 40 ps MIPI/DPHY SID1449 fPX_BGA Pixel clock frequency – – 220 MHz SID1417 VCMRX Common-mode voltage HS receive mode 70 – 330 mV SID1418 VIDTH Differential input HIGH threshold 70 – – mV SID1419 VIDTL Differential Input LOW threshold – – –70 mV SID1420 VIHHS Single-ended input HIGH voltage – – 460 mV SID1421 VILHS Single-ended Input LOW voltage –40 – – mV SID1422 ZID Differential Input Impedance 80 – 125 Ω SID1423 VIH_LS Logic 1 input voltage LS – – 880 mV SID1424 VIL_LS Logic 0 Input voltage LS 550 – – mV SID1425 VHYST Input hysteresis 25 – – mV SID1426 ILEAK Pin leakage current DPx, DNx, CLKP/N in LP mode –100 – 100 µA TA = 85°C SID1427 IVDDA_LP Current in LP – – 3 mA SID1428 IVDDA_PD Current when D-PHY powered down – 8 800 µA Typ: TA = 25°C, VDDA_MIPI = 1.15 V, process typ (TT) Max: TA = 105°C, VDDA_MIPI = 1.21 V, process worst (FF) SID1428_1 IVDDA_PD_1 Current when D-PHY powered down (room temp) – – 20 µA Max: TA = 25°C, VDDA_MIPI = 1.15 V (max VREG), process worst (FF) SID1428_2 IVDDA_PD_2 Current when D-PHY powered down – – 150 µA Max: TA = 85°C, VDDA_MIPI = 1.15 V (max VREG), process worst (FF) SID1429 IVDDA_ULP Current in ULP – – 2 mA SID1430 IVDDA_HS current in HS – – 35 mA SID1431 tCLK_TERM_EN Time for the Clock Lane receiver to enable the HS line termination, starting from the time point when Dn crosses VIL,MAX – – 38 ns SID1432 tD_TERM_EN Time for the Data Lane receiver to enable the HS line termination, starting from the time point when Dn crosses, VIL,MAX – – 38 ns SID1433 tCLK_SETTLE Time interval during which HS receiver should ignore any Clock Lane HS transitions, starting from the beginning of TCLK-PREPARE 95 – 300 ns SID1434 tHS_SETTTLE Time interval during which the HS receiver shall ignore any DATA Lane HS transitions, starting from the beginning of THSPREPARE. The HS receiver shall ignore any Data Lane transitions before minimum value, and the HS receiver shall respond to any Data Lane transitions after maximum value 85 + 6 × UI – 145 + 10 × UI ns Table 26-39 Graphics specifications (continued) Spec ID Parameter Description Min Typ Max Units Details/Conditions |
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