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CYT4DNJBJS bảng dữ liệu(PDF) 183 Page - Infineon Technologies AG

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Giải thích chi tiết về linh kiện  TRAVEO™ T2G 32-bit Automotive MCU Based on Arm® Cortex®-M7 dual
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Datasheet
183
002-24601 Rev. *I
2023-02-14
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
Figure 26-8
TTL display out timing
Figure 26-9
Video capture timing
SID1435
tHS-SKIP
Time interval during which the
HS-RX should ignore any transi-
tions on the Data Lane, following a
HS burst. The end point of the
interval is defined as the beginning
of the LP-11 state following the HS
burst.
40
–
55 +
4 × UI
ns
SID1436
VΔVCMRX_HF
Common-mode interference
–
–
100
mV
Beyond 450 MHz
SID1437
VΔVCMRX_LF
Common-mode interference
–
–
50
mV
50 to 450 MHz
SID1438
CCM
Common Mode termination
–
–
60
pF
SID1439
tE_SPIKE
Input pulse rejection
–
–
300
ps
SID1440
tMIN_RX
Minimum pulse width response
–
–
20
ns
SID1443
tSETUP_BGA
Data to Clock setup time
0.2
–
–
UI
SID1444
tHOLD_BGA
Clock to Data told time
0.2
–
–
UI
SID1445
IVDDA_1P4GBPS_HS
Current in high speed max
frequency
–
–
35
mA
SID1446
IVDDA_10M_LP
Current in LP mode max frequency
–
–
2
mA
Table 26-39
Graphics specifications (continued)
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
tDC1CYC
tDC1S
tDC1H
VOH
DSP1_CLK
DSP1_DATA0_11-0
DSP1_DATA1_11-0
DSP1_CTRL2_0
Valid
VOH
tCAP0CYC
tCAP0SU
CAP0_CLK
CAP0_DATA[35-0]
Valid
tCAP0HD
VIH
VIL
VIH
VIH
VIH



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