CYT4DNJBJS datasheet(168/209 Pages) INFINEON

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Datasheet

168

002-24601 Rev. *I

2023-02-14

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Electrical specifications

SID1001

tHC

Serial clock high

time

0.35 ×

tSCLK

–

ns Guaranteed by design

SID1002

tLC

Serial clock low

time

0.35 ×

tSCLK

–

ns Guaranteed by design

SID1010

tMCLK

Master clock input

period

–

ns MCLK must be SCLK*2; The

maximum output frequency of

the TDM depends on the used I/O

type.

SID1002A tMCLK

Master clock output

period

–

ns For TDM channels on

HSIO_STDLN type I/Os

SID1002B tMCLK

Master clock output

period

–

ns For TDM channels on GPIO_STD,

GPIO_ENH type I/Os

SID1002C tMCLK

Master clock output

period

–

ns For TDM channels on GPIO_SMC

type I/Os

SID1002D tMCLK_IH

Master clock input

high time

0.45 ×

tMCLK

–

SID1002E

tMCLK_IL

Master clock input

low time

0.45 ×

tMCLK

–

SID1002F

tMCLK_OH

Master clock output

high time

0.35 ×

tMCLK

–

ns Only if internal clock source,

divided EXT_CLK input, or

EXT_CLK input on HSIO_STDLN is

used

SID1002G tMCLK_OL

Master clock output

low time

0.35 ×

tMCLK

–

ns Only if internal clock source,

divided EXT_CLK input, or

EXT_CLK input on HSIO_STDLN is

used

TDM Transmit Timing

SID1003

tDTR

Delay from rising

edge of TX_CLK to

transition on

TX_SD/TX_FSYNC

(WS)

–

0.8 ×

tSCLK

ns Guaranteed by design

SID1004

tHTR

Delay from rising

edge of TX_CLK to

transition on

TX_SD/TX_FSYNC

(WS)

–

ns Guaranteed by design

SID1011

tHR_WS_POL_0 TX Slave: Hold on

TX_FSYNC (WS)

after the 1st edge

following the

driving edge of

TX_CLK (SCK_POLARITY

= 0, half-cycle hold)

1.8

–

SID1012

tHR_WS_POL_1 TX Slave: Hold on

TX_FSYNC (WS)

after the 2nd edge

following the

driving edge of

TX_CLK (SCK_POLARITY

= 1, zero-cycle hold)

1.8

–

Table 26-33

Sound subsystem specifications (continued)

Spec ID

Parameter

Description

Min

Typ

Max

Units

Details/conditions

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