CYT4DNJBJS datasheet(167/209 Pages) INFINEON

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Datasheet

167

002-24601 Rev. *I

2023-02-14

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Electrical specifications

SID753

tSCLK_TRANS

SCLK transition timing

–

20% to 80%

SID754

tMCLK_TRANS

MCLK transition timing

–

20% to 80%

SID755

tDATA_TRANS

DATA transition timing

–

20% to 80%

TDM I/O Settings

Recommended I/O configuration:

For serial clock above 25 MHz

HSIO_STDLN: CFG_DRIVE_EXT<1:0>/DRIVE_SEL_EXT<2:0> = 0b011, CFG_IN_AUTOLVL/VTRIP_SEL<0:0>= 0b0, CFG_IN/VTRIP_SEL<0:0> = 0b1, CFG_SLEW_EXT/SLEW<0:0> = 0b0

For serial clock in between 12.5 MHz, and 25 MHz

GPIO_STD: CFG_OUT/DRIVE_SEL<1:0> = 0b01, CFG_IN_AUTOLVL/VTRIP_SEL<0:0>= 0b0, CFG_IN/VTRIP_SEL<0:0> = 0b1

GPIO_ENH: CFG_OUT/DRIVE_SEL<1:0> = 0b01, CFG_IN_AUTOLVL/VTRIP_SEL<0:0>= 0b0, CFG_IN/VTRIP_SEL<0:0> = 0b1, CFG_OUT/SLOW<0:0> = 0b0

For serial clock up to 25 MHz

HSIO_STDLN: CFG_DRIVE_EXT<1:0>/DRIVE_SEL_EXT<2:0> = 0b100, CFG_IN_AUTOLVL/VTRIP_SEL<0:0>= 0b0, CFG_IN/VTRIP_SEL<0:0> = 0b1, CFG_SLEW_EXT/SLEW<0:0> = 0b0

For serial clock up to 12.5 MHz

GPIO_STD: CFG_OUT/DRIVE_SEL<1:0> = 0b01, CFG_IN_AUTOLVL/VTRIP_SEL<0:0>= 0b0, CFG_IN/VTRIP_SEL<0:0> = 0b1

GPIO_ENH: CFG_OUT/DRIVE_SEL<1:0> = 0b01, CFG_IN_AUTOLVL/VTRIP_SEL<0:0>= 0b0, CFG_IN/VTRIP_SEL<0:0> = 0b1, CFG_OUT/SLOW<0:0> = 0b0

GPIO_SMC: CFG_OUT/DRIVE_SEL<1:0> = 0b01, CFG_IN_AUTOLVL/VTRIP_SEL<0:0>= 0b0, CFG_IN/VTRIP_SEL<0:0> = 0b1

TDM Serial Clock

SID1000B tSCLK

Serial clock period,

TDM[x]

(x=0 through 3)

–

ns Guaranteed by Design

TX Master:

TX_IF_CTL.SCK_POLARITY = 0

RX Master:

RX_IF_CTL.LATE_SAMPLE = 1

RX_IF_CTL.LATE_CAPTURE =

0b00

TX Slave:

Set TX_IF_CTL.SCK_POLARITY = 1

RX Slave:

RX_IF_CTL.SCK_POLARITY= 0

For TDM channels on GPIO_STD,

GPIO_ENH, HSIO_STDLN, type

IO-cells

SID1000D tSCLK

Serial clock period,

TDM[x]

(x=0 through 3)

–

ns Guaranteed by Design

TX Master:

TX_IF_CTL.SCK_POLARITY = 0

RX Master:

RX_IF_CTL.LATE_SAMPLE = 1

RX_IF_CTL.LATE_CAPTURE =

0b00

TX Slave:

Set TX_IF_CTL.SCK_POLARITY = 1

RX Slave:

RX_IF_CTL.SCK_POLARITY = 0

SID1000E

tSCLK

Serial clock period,

TDM[x]

(x=0 through 1)

–

ns Guaranteed by Design

TX Master:

TX_IF_CTL.SCK_POLARITY = 0

RX Master:

not supported at 50MHz

TX Slave:

not supported at 50MHz

RX Slave:

not supported at 50MHz

For TDM channels on

HSIO_STDLN type IO-cells

Table 26-33

Sound subsystem specifications (continued)

Spec ID

Parameter

Description

Min

Typ

Max

Units

Details/conditions

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