CYT4DNJBJS datasheet(166/209 Pages) INFINEON

166 / 209 page

Datasheet

166

002-24601 Rev. *I

2023-02-14

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Electrical specifications

26.12

Sound subsystem specifications

Table 26-33

Sound subsystem specifications

Spec ID

Parameter

Description

Min

Typ

Max

Units

Details/conditions

I2S I/O settings

Recommended I/O configuration:

HSIO_STDLN: CFG_DRIVE_EXT<1:0>/DRIVE_SEL_EXT<2:0> =0b100, CFG_IN_AUTOLVL/VTRIP_SEL<0:0>= 0b0, CFG_IN/VTRIP_SEL<0:0> = 0b1, CFG_SLEW_EXT/SLEW<2:0>

=0b000

GPIO_STD: CFG_OUT/DRIVE_SEL<1:0> =0b01, CFG_IN_AUTOLVL/VTRIP_SEL<0:0>= 0b0, CFG_IN/VTRIP_SEL<0:0> = 0b1

GPIO_ENH: CFG_OUT/DRIVE_SEL<1:0> =0b01, CFG_IN_AUTOLVL/VTRIP_SEL<0:0>= 0b0, CFG_IN/VTRIP_SEL<0:0> = 0b1, CFG_OUT/SLOW<0:0> =0b0

GPIO_SMC: CFG_OUT/DRIVE_SEL<1:0> =0b01, CFG_IN_AUTOLVL/VTRIP_SEL<0:0>= 0b0, CFG_IN/VTRIP_SEL<0:0> = 0b1

I2S Serial Clock Frequency

SID796

tSCLK

Serial clock period

162

–

ns Guaranteed by design

No feature is used for low

frequency I2S operation:

DUT RX Master:

* RX_IF_CTL.LATE_SAMPLE = 0

* RX_IF_CTL.LATE_CAPTURE =

0b00

DUT TX Slave: No special

configuration

DUT RX Slave:

* RX_IF_CTL.LATE_SAMPLE = 0

SID797

tHC

Serial clock high

time

0.35 ×

tSCLK

–

ns Guaranteed by design

SID798

tLC

Serial clock low

time

0.35 ×

tSCLK

–

ns Guaranteed by design

SID799

tMCLK

Master clock period

–

ns Guaranteed by design

I2S Transmitter Timing

SID740

tDTR

Delay from rising

edge of TX_CLK to

transition on

TX_SD/TX_FSYNC

(WS)

–

0.8 ×

tSCLK

ns Guaranteed by design

SID741

tHTR

Delay from rising

edge of TX_CLK to

transition on

TX_SD/TX_FSYNC

(WS)

–

ns Guaranteed by design

SID743

tHR_WS_POL_0 TX Slave: Hold on

TX_FSYNC (WS) after

the 1st edge following

the driving edge of

TX_CLK (SCK_PO-

LARITY = 0, half-cycle

hold)

1.8

–

I2S Receiver Timing

SID751

tSR

Setup on

RX_SD/RX_FSYNC

(WS) before the

rising edge to

RX_CLK

0.2 ×

tSCLK

–

ns Guaranteed by Design

Setup time is independent from

RX_IF_CTL.LATE_SAMPLE,

RX_IF_CTL.LATE_CAPTURE or

SCK_POLARITY setting

SID752A

tHR

Hold on

RX_SD/RX_FSYNC

(WS) after the rising

edge to RX_CLK

1.8

–

ns Guaranteed by Design

Sampling edge w.r.t driving edge

of RX_SCLK: 1st edge (0.5 x tSCLK)

RX-Master:

RX_IF_CTL.LATE_SAMPLE = 0,

RX_IF_CTL.LATE_CAPTURE =

0b00

RX-Slave: SCK_POLARITY = 0

CYT4DNJBJS bảng dữ liệu(PDF) 166 Page - Infineon Technologies AG

CYT4DNJBJS bảng dữ liệu(HTML) 166 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL