CYT4DNJBJS datasheet(130/209 Pages) INFINEON

130 / 209 page

Datasheet

130

002-24601 Rev. *I

2023-02-14

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Electrical specifications

SID195

tVSS

SPI Master: MOSI valid after

SSEL falling edge (CPHA=0)

–

SPI Master (Full-clock

mode:LATE_MISO_SAMPLE

= 1) – 12.5 Mbps

for instances on GPIO_STD,

GPIO_ENH, GPIO_SMC

SID196

tDHI

SPI Master: MISO hold time

after SCLK capturing edge

–

–ns

SPI Master (Full-clock

mode:LATE_MISO_SAMPLE

= 1) – 12.5 Mbps

for instances on GPIO_STD,

GPIO_ENH, GPIO_SMC

SID198

tEN_SETUP

SSEL valid, before the first

SCLK

capturing edge

0.5 ×

(1/fSPI)

–

–ns

Min is half clock period

SID199

tEN_SHOLD

SSEL hold, after the last SCLK

capturing edge

0.5 ×

(1/fSPI)

–

–ns

Min is half clock period

SID197

CSPIM_MS

SPI Capacitive Load

–

SPI Interface Master (Full-clock mode: LATE_MISO_SAMPLE = 1, HSIO)

SID190A fSPI

SPI operating frequency

–

–20

MHz Donotusehalf-clockmode:

LATE_MISO_SAMPLE = 0

SPI Master (Full-clock

mode:LATE_MISO_SAMPLE

= 1) - 20 Mbps

For 20 Mbps, SCB operating

frequency (fSCB) must be

configured to 80 MHz.

for instances on HSIO_STD

SID191A tDMO

SPI Master: MOSI valid after

SCLK driving edge

–

–9

SPI Master (Full-clock

mode:LATE_MISO_SAMPLE

= 1) – 20 Mbps

For 20 Mbps, SCB operating

frequency (fSCB) must be

configured to 80 MHz

for instances on HSIO_STD

SID192A tDSI

SPI Master: MISO valid

before SCLK capturing edge

–

–ns

SPI Master (Full-clock

mode:LATE_MISO_SAMPLE

= 1) – 20 Mbps

For 20 Mbps, SCB operating

frequency (fSCB) must be

configured to 80 MHz

for instances on HSIO_STD

SID193A tHMO

SPI Master: Previous MOSI

data hold time

–

–ns

SPI Master (Full-clock

mode:LATE_MISO_SAMPLE

= 1) – 20 Mbps

For 20 Mbps, SCB operating

frequency (fSCB) must be

configured to 80 MHz

for instances on HSIO_STD

SID194A tW_SCLK_H_L SPI SCLK pulse width HIGH

or LOW

0.4 ×

(1/fSPI)

0.5 ×

(1/fSPI)

0.6 ×

(1/fSPI)

SPI Master (Full-clock

mode:LATE_MISO_SAMPLE

= 1) – 20 Mbps

For 20 Mbps, SCB operating

frequency (fSCB) must be

configured to 80 MHz

for instances on HSIO_STD

SID195A tVSS

SPI Master: MOSI valid after

SSEL falling edge (CPHA=0)

–

SPI Master (Full-clock

mode:LATE_MISO_SAMPLE

= 1) – 20 Mbps

For 20 Mbps, SCB operating

frequency (fSCB) must be

configured to 80 MHz

for instances on HSIO_STD

Table 26-10

Serial Communication Block (SCB) specifications (continued)

Spec ID Parameter

Description

Min

Typ

Max Units

Details/conditions

CYT4DNJBJS bảng dữ liệu(PDF) 130 Page - Infineon Technologies AG

CYT4DNJBJS bảng dữ liệu(HTML) 130 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL