CYT4DNJBJS datasheet(132/209 Pages) INFINEON

132 / 209 page

Datasheet

132

002-24601 Rev. *I

2023-02-14

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Electrical specifications

SID222

tDSO_EXT

SPI Slave: MISO Valid after

SCLK

driving edge, in the

external-clocked mode

–

–30

SPI Slave, externally

clocked: 12.5 Mbps

SID223

tHSO_EXT

SPI Slave: Previous MISO

data hold time

–

–ns

SPI Slave, externally

clocked: 12.5 Mbps

SID224

tEN_SET-

UP_EXT

SPI Slave: SSEL valid to first

SCLK

valid edge

–

–ns

SPI Slave, externally

clocked: 12.5 Mbps

SID225

tEN_HOLD_EXT SPI Slave Select active

(LOW) from last SCLK hold

–

–ns

SPI Slave, externally

clocked: 12.5 Mbps

SID226

tW_DIS_EXT

SPI Slave Select inactive

time

–

–ns

SPI Slave, externally

clocked: 12.5 Mbps

SID227

tW_SCLKH_EXT SPI SCLK pulse width HIGH

–

–ns

SPI Slave, externally

clocked: 12.5 Mbps

SID228

tW_SCLKL_EXT SPI SCLK pulse width LOW

–

–ns

SPI Slave, externally

clocked: 12.5 Mbps

SID229

tSIH_EXT

SPI MOSI hold from SCLK

–

–ns

SPI Slave, externally

clocked: 12.5 Mbps

SID230

CSPIS_EXT

SPI Capacitive Load

–

–20

pF SPI Slave, externally

clocked: 12.5 Mbps

SID231

tVSS_EXT

SPI Slave: MISO valid after

SSEL falling edge (CPHA = 0)

–

–33

SPI Slave, externally

clocked: 12.5 Mbps

SPI Interface Slave (internally clocked, SMC I/O)

SID205_2 fSPI_INT

SPI operating frequency

–

12.5

MHz SPISlave,internallyclocked

SID206_2 tDMI_INT

SPI Slave: MOSI Valid before

SCLK

capturing edge

–

–ns

SPI Slave, internally clocked

SID207_2 tDSO_INT

SPI Slave: MISO Valid after

SCLK

driving edge, in the

internal-clocked mode

–

SPI Slave, internally clocked

SID208_2 tHSO_INT

SPI Slave: Previous MISO

data hold time

–

–ns

SPI Slave, internally clocked

SID209_2 tEN_SET-

UP_INT

SPI Slave: SSEL valid to first

SCLK

valid edge

–

–ns

SPI Slave, internally clocked

SID210_2 tEN_HOLD_INT SPI Slave Select active

(LOW) from last SCLK hold

–

–ns

SPI Slave, internally clocked

SID211_2 tEN_SET-

UP_PRE

SPI Slave: from SSEL valid,

to SCLK falling edge before

the first data bit

–

–ns

SPI Slave, internally clocked

SID212_2 tEN_HOLD_PRE SPI Slave: from SCLK falling

edge before the first data

bit, to SSEL invalid

–

–ns

SPI Slave, internally clocked

SID213_2 tEN_SETUP_CO SPI Slave: from SSEL valid,

toSCLKfallingedgeinthefirst

data bit

–

–ns

SPI Slave, internally clocked

SID214_2 tEN_HOLD_CO SPI Slave: from SCLK falling

edge in the first data bit, to

SSEL invalid

–

–ns

SPI Slave, internally clocked

SID215_2 tW_DIS_INT

SPI Slave Select inactive

time

–

–ns

SPI Slave, internally clocked

SID216_2 tW_SCLKH_INT SPI SCLK pulse width HIGH

–

–ns

SPI Slave, internally clocked

Table 26-10

Serial Communication Block (SCB) specifications (continued)

Spec ID Parameter

Description

Min

Typ

Max Units

Details/conditions

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