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CYT4DNJBJS bảng dữ liệu(PDF) 133 Page - Infineon Technologies AG |
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CYT4DNJBJS bảng dữ liệu(HTML) 133 Page - Infineon Technologies AG |
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133 / 209 page  Datasheet 133 002-24601 Rev. *I 2023-02-14 TRAVEO™ T2G 32-bit Automotive MCU Based on Arm® Cortex®-M7 dual Electrical specifications SID217_2 tW_SCLKL_INT SPI SCLK pulse width LOW 36 – –ns SPI Slave, internally clocked SID218_2 tSIH_INT SPI MOSI hold from SCLK 20 – –ns SPI Slave, internally clocked SID219_2 CSPIS_INT SPI Capacitive Load – – 20 pF SPISlave,internallyclocked SPI Interface Slave (externally clocked, SMC I/O) SID220_2 fSPI_EXT SPI operating frequency – – 12.5 MHz SPI Slave, externally clocked: 12.5 Mbps SID221_2 tDMI_EXT SPI Slave: MOSI Valid before SCLK capturing edge 8 – –ns SPI Slave, externally clocked: 12.5 Mbps SID222_2 tDSO_EXT SPI Slave: MISO Valid after SCLK driving edge, in the external-clocked mode – –34 ns SPI Slave, externally clocked: 12.5 Mbps SID223_2 tHSO_EXT SPI Slave: Previous MISO data hold time 5 – –ns SPI Slave, externally clocked: 12.5 Mbps SID224_2 tEN_SET- UP_EXT SPI Slave: SSEL valid to first SCLK valid edge 20 – –ns SPI Slave, externally clocked: 12.5 Mbps SID225_2 tEN_HOLD_EXT SPI Slave Select active (LOW) from last SCLK hold 20 – –ns SPI Slave, externally clocked: 12.5 Mbps SID226_2 tW_DIS_EXT SPI Slave Select inactive time 20 – –ns SPI Slave, externally clocked: 12.5 Mbps SID227_2 tW_SCLKH_EXT SPI SCLK pulse width HIGH 36 – –ns SPI Slave, externally clocked: 12.5 Mbps SID228_2 tW_SCLKL_EXT SPI SCLK pulse width LOW 36 – –ns SPI Slave, externally clocked: 12.5 Mbps SID229_2 tSIH_EXT SPI MOSI hold from SCLK 5 – –ns SPI Slave, externally clocked: 12.5 Mbps SID230_2 CSPIS_EXT SPI Capacitive Load – –20 pF SPI Slave, externally clocked: 12.5 Mbps SID231_2 tVSS_EXT SPI Slave: MISO valid after SSEL falling edge (CPHA = 0) – –37 ns SPI Slave, externally clocked: 12.5 Mbps SPI Interface Slave (externally clocked, 20 MHz) SID220A fSPI_EXT SPI operating frequency – –20 MHz SPI Slave, externally clocked: 20 Mbps SID221A tDMI_EXT SPI Slave: MOSI Valid before SCLK capturing edge 5 – –ns SPI Slave, externally clocked: 20 Mbps SID222A tDSO_EXT SPI Slave: MISO Valid after SCLK driving edge, in the external-clocked mode – –18 ns SPI Slave, externally clocked: 20 Mbps SID223A tHSO_EXT SPI Slave: Previous MISO data hold time 5 – –ns SPI Slave, externally clocked: 20 Mbps SID224A tEN_SET- UP_EXT SPI Slave: SSEL valid to first SCLK valid edge 20 – –ns SPI Slave, externally clocked: 20 Mbps SID225A tEN_HOLD_EXT SPI Slave Select active (LOW) from last SCLK hold 20 – –ns SPI Slave, externally clocked: 20 Mbps SID226A tW_DIS_EXT SPI Slave Select inactive time 20 – –ns SPI Slave, externally clocked: 20 Mbps SID227A tW_SCLKH_EXT SPI SCLK pulse width HIGH 20 – –ns SPI Slave, externally clocked: 20 Mbps SID228A tW_SCLKL_EXT SPI SCLK pulse width LOW 20 – –ns SPI Slave, externally clocked: 20 Mbps Table 26-10 Serial Communication Block (SCB) specifications (continued) Spec ID Parameter Description Min Typ Max Units Details/conditions |
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