CYT4DNJBJS datasheet(129/209 Pages) INFINEON

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Datasheet

129

002-24601 Rev. *I

2023-02-14

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Electrical specifications

SID176

tSU;DAT

Data setup time

–

–ns

SID178

Fall time of SCL and SDA

20 ×

(VDDIO_GPIO

/5.5)

–

160

Input and output, 20pF load

Output: Only for GPIO_ENH

SID179

tSU;STO

Setup time for STOP

260

–

–ns

SID180

tBUF

Bus free time between

START and STOP

500

–

–ns

SID181

Capacitive load for each bus

line

–

–20

SID182

tVD;DAT

Time for data signal from

SCL LOW to SDA output

–

450

SID183

tVD;ACK

Data valid acknowledge

time

–

450

SID184

tSP

Pulse width of spikes that

must be suppressed by the

input filter

–

–50

SPI Interface

Recommended I/O Configuration: (Applicable to all below SPI modes)

HSIO_STDLN: CFG_DRIVE_EXT<1:0>/DRIVE_SEL_EXT<2:0> = 0b010, CFG_IN_AUTOLVL/VTRIP_SEL<0:0>= 0b0, CFG_IN/VTRIP_SEL<0:0> = 0b0

For SPI speeds ≤ 12.5 MHz

GPIO_STD: CFG_OUT/DRIVE_SEL<1:0> = 0b10, CFG_IN_AUTOLVL/VTRIP_SEL<0:0>= 0b0, CFG_IN/VTRIP_SEL<0:0> = 0b0

GPIO_ENH: CFG_OUT/DRIVE_SEL<1:0> = 0b10, CFG_IN_AUTOLVL/VTRIP_SEL<0:0>= 0b0, CFG_IN/VTRIP_SEL<0:0> = 0b0, CFG_OUT/SLOW<0:0> = 0b0

GPIO_SMC: CFG_OUT/DRIVE_SEL<1:0> = 0b10, CFG_IN_AUTOLVL/VTRIP_SEL<0:0>= 0b0, CFG_IN/VTRIP_SEL<0:0> = 0b0, CFG_OUT/SLOW<0:0> = 0b0

SPI Interface Master (Full-clock mode: LATE_MISO_SAMPLE = 1, GPIO)

SID190

fSPI

SPI operating frequency

–

12.5

MHz Donotusehalf-clockmode:

LATE_MISO_SAMPLE = 0

SPI Master (Full-clock

mode:LATE_MISO_SAMPLE

= 1) – 12.5 Mbps

for instances on GPIO_STD,

GPIO_ENH, GPIO_SMC

SID191

tDMO

SPI Master: MOSI valid after

SCLK driving edge

–

–15

SPI Master (Full-clock

mode:LATE_MISO_SAMPLE

= 1) – 12.5 Mbps

for instances on GPIO_STD,

GPIO_ENH, GPIO_SMC

SID192

tDSI

SPI Master: MISO valid

before SCLK capturing edge

–

–ns

SPI Master (Full-clock

mode:LATE_MISO_SAMPLE

= 1) – 12.5 Mbps

for instances on GPIO_STD,

GPIO_ENH, GPIO_SMC

SID193

tHMO

SPI Master: Previous MOSI

data hold time

–

–ns

SPI Master (Full-clock

mode:LATE_MISO_SAMPLE

= 1) – 12.5 Mbps

for instances on GPIO_STD,

GPIO_ENH, GPIO_SMC

SID194

tW_SCLK_H_L SPI SCLK pulse width HIGH

or LOW

0.4 ×

(1/fSPI)

0.5 ×

(1/fSPI)

0.6 ×

(1/fSPI)

SPI Master (Full-clock

mode:LATE_MISO_SAMPLE

= 1) – 12.5 Mbps

for instances on GPIO_STD,

GPIO_ENH, GPIO_SMC

Table 26-10

Serial Communication Block (SCB) specifications (continued)

Spec ID Parameter

Description

Min

Typ

Max Units

Details/conditions

Notes

71.In order to drive full bus load at 400 kHz, 6 mA IOL is required at 0.6 V VOL.

72.In order to drive full bus load at 1 MHz, 20 mA IOL is required at 0.4 V VOL.

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