CYT4DNJBJS datasheet(127/209 Pages) INFINEON

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Datasheet

127

002-24601 Rev. *I

2023-02-14

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Electrical specifications

Figure 26-8

TCPWM timing diagrams

Table 26-10

Serial Communication Block (SCB) specifications

Spec ID Parameter

Description

Min

Typ

Max Units

Details/conditions

SID129

fSCB

SCB operating frequency

––

100

MHz

SID129_2 tSPI_TRANS

SCB transition in SPI mode

––

I2C Interface-Standard-mode

Recommended I/O Configuration:

GPIO_STD: CFG_OUT/DRIVE_SEL<1:0> = 0b10, CFG_IN_AUTOLVL/VTRIP_SEL<0:0>= 0b0, CFG_IN/VTRIP_SEL<0:0> = 0b0, CFG/DRIVE_MODE<2:0> = 0b100

GPIO_ENH: CFG_OUT/DRIVE_SEL<1:0> = 0b00, CFG_IN_AUTOLVL/VTRIP_SEL<0:0>= 0b0, CFG_IN/VTRIP_SEL<0:0> = 0b0, CFG/DRIVE_MODE<2:0> = 0b100, CFG_OUT/SLOW<0:0>

= 0b1

GPIO_SMC: CFG_OUT/DRIVE_SEL<1:0> = 0b10, CFG_IN_AUTOLVL/VTRIP_SEL<0:0>= 0b0, CFG_IN/VTRIP_SEL<0:0> = 0b0, CFG/DRIVE_MODE<2:0> = 0b100, CFG_OUT/SLOW<0:0>

= 0b0

HSIO_STDLN: CFG_DRIVE_EXT<1:0>/DRIVE_SEL_EXT<2:0> = 0b010, CFG_IN_AUTOLVL/VTRIP_SEL<0:0>= 0b0, CFG_IN/VTRIP_SEL<0:0> = 0b0, CFG/DRIVE_MODE<2:0> =0b100,

CFG_SLEW_EXT/SLEW<2:0> =0b000

(Note: SID138 is not valid for HSIO_STDLN)

SID130

fSCL

SCL clock frequency

–

100

kHz

SID131

tHD;STA

Hold time, START condition

4000

–

–ns

SID132

tLOW

Low period of SCL

4700

–

–ns

SID133

tHIGH

High period of SCL

4000

–

–ns

SID134

tSU;STA

Setup time for a repeated

START

4700

–

–ns

SID135

tHD;DAT

Data hold time, for receiver

–

–ns

SID136

tSU;DAT

Data setup time

250

–

–ns

SID138

Fall time of SCL and SDA

–

300

Input and output

Output: Only valid for

GPIO_ENH, GPIO_SMC,

GPIO_STD

SID139

tSU;STO

Setup time for STOP

4000

–

–ns

SID140

tBUF

Bus-free time between

START and STOP

4700

–

–ns

SID141

Capacitive load for each bus

line

–

400

SID142

tVD;DAT

Time for data signal from

SCL LOW to SDA output

–

3450

SID143

tVD;ACK

Data valid acknowledge

time

–

3450

TCPWM Timing Diagrams

Input Signal

1: tPWMENEXT, tQRES

2: tPWMEXT

VIL

VIH

Output Signal

VOL

VOH

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